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[RACL] Parse mappings and auto-connect RACL #4268

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[RACL] Parse mappings and auto-connect RACL

[RACL] Parse mappings and auto-connect RACL #4268

Triggered via pull request January 10, 2025 15:03
@Razer6Razer6
synchronize #25749
Razer6:racl-connections
Status Failure
Total duration 3h 31m 5s
Artifacts 5

ci.yml

on: pull_request
Lint (quick)
3m 22s
Lint (quick)
Earl Grey for CW310 Hyperdebug  /  Build bitstream
6m 22s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
6m 28s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
6m 20s
Earl Grey for CW340 / Build bitstream
Lint (slow)
9m 45s
Lint (slow)
Build documentation
5m 29s
Build documentation
Airgapped build
7m 54s
Airgapped build
Verible lint
1m 0s
Verible lint
Run OTBN smoke Test
1m 38s
Run OTBN smoke Test
Run OTBN crypto tests
21m 13s
Run OTBN crypto tests
Verilated English Breakfast
53s
Verilated English Breakfast
Verilated Earl Grey
3m 58s
Verilated Earl Grey
CW305's Bitstream
6m 1s
CW305's Bitstream
Build Docker Containers
2m 45s
Build Docker Containers
Build and test software
18m 53s
Build and test software
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
25s
Verify FPGA jobs
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19 errors
Verilated English Breakfast
Process completed with exit code 1.
Run OTBN smoke Test
Process completed with exit code 1.
Verilated Earl Grey
Process completed with exit code 1.
CW305's Bitstream
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Verilog style lint of design sources with Verible failed. Run 'util/dvsim/dvsim.py -t veriblelint hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson' and fix all errors.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
Earl Grey for CW310 / Build bitstream
Process completed with exit code 1.
Earl Grey for CW310 Hyperdebug / Build bitstream
Process completed with exit code 1.
Earl Grey for CW340 / Build bitstream
Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.
Verify FPGA jobs
Process completed with exit code 1.

Artifacts

Produced during runtime
Name Size
chip_earlgrey_cw310-build-out
46.9 KB
chip_earlgrey_cw310_hyperdebug-build-out
48.1 KB
chip_earlgrey_cw340-build-out
46.9 KB
sw_build_test-test-results
71.8 KB
verilator_earlgrey-test-results
201 Bytes