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[RACL] Add RACL support for windows and enable RACL for mbx and spi_host. #4920

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[RACL] Add RACL support for windows and enable RACL for mbx and spi_host.

[RACL] Add RACL support for windows and enable RACL for mbx and spi_host. #4920

Triggered via pull request January 24, 2025 13:22
@davidschrammeldavidschrammel
synchronize #26004
davidschrammel:racl-window
Status Cancelled
Total duration 44m 35s
Artifacts 3

ci.yml

on: pull_request
Lint (quick)
3m 4s
Lint (quick)
Earl Grey for CW310  /  Build bitstream
0s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW310 Hyperdebug  /  Build bitstream
0s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
0s
Earl Grey for CW340 / Build bitstream
Lint (slow)
7m 8s
Lint (slow)
Build documentation
4m 33s
Build documentation
Airgapped build
9m 32s
Airgapped build
Verible lint
1m 11s
Verible lint
Run OTBN smoke Test
2m 26s
Run OTBN smoke Test
Run OTBN crypto tests
2m 43s
Run OTBN crypto tests
Verilated English Breakfast
7m 54s
Verilated English Breakfast
Verilated Earl Grey
41m 12s
Verilated Earl Grey
CW305's Bitstream
25m 43s
CW305's Bitstream
Build Docker Containers
2m 17s
Build Docker Containers
Build and test software
17m 8s
Build and test software
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
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Verify FPGA jobs
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16 errors
Lint (slow)
Auto-generated Register headers not up-to-date. Regenerate with 'make -k -C hw regs'.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Build and test software
Process completed with exit code 1.
Earl Grey for CW340 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26004/merge' exists
Earl Grey for CW310 Hyperdebug / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26004/merge' exists
Earl Grey for CW310 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26004/merge' exists
Earl Grey for CW310 / Build bitstream
A task was canceled.
Verilated Earl Grey
Canceling since a higher priority waiting request for 'CI-refs/pull/26004/merge' exists
Verilated Earl Grey
The operation was canceled.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.4 MB
sw_build_test-test-results
72 KB
verilated_englishbreakfast
7.03 MB