[englishbreakfast] Convert to ordinary topgen flow

Convert englishbreakfast to use the ordinary topgen flow. Commit the
generated code like other tops.

Remove the fileset_top and fileset_topgen flags, in addition to the
topgen-fusesoc.py script.

The fileset_top and fileset_topgen flags are now completely unused,
since all the IPs that once depended on them have been reimplemented as
ipgen cores. Remove the cruft.

Signed-off-by: Alexander Williams <[email protected]>

.gitignore

@@ -64,13 +64,6 @@ hw/foundry/
 # ROM_EXT signer vendored in dependencies
 sw/host/rom_ext_image_signer/vendored_dependencies
 
-# Autogen files for non-Earlgrey tops
-hw/top_englishbreakfast/**/autogen/
-hw/top_englishbreakfast/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
-hw/top_englishbreakfast/ip/sensor_ctrl/rtl/*
-hw/top_englishbreakfast/ip/xbar_main/xbar_main.core
-hw/top_englishbreakfast/ip/xbar_peri/xbar_peri.core
-
 # Rust Cargo build system files.
 sw/host/**/target
 rust-project.json

BUILD.bazel

@@ -14,8 +14,6 @@ filegroup(
     name = "cores",
     srcs = [
         "check_tool_requirements.core",
-        "topgen.core",
-        "topgen-reg-only.core",
     ],
 )
 

ci/scripts/build-bitstream-vivado.sh

@@ -26,12 +26,10 @@ case x"$TOPLEVEL" in
     xtop_earlgrey)
         HAS_SCRAMBLED_ROM=1
         HAS_OTP=1
-        RUN_TOPGEN_FUSESOC=0
         ;;
     xtop_englishbreakfast)
         HAS_SCRAMBLED_ROM=0
         HAS_OTP=0
-        RUN_TOPGEN_FUSESOC=1
         ;;
     *)
         usage "Unknown toplevel: $TOPLEVEL"
@@ -86,17 +84,10 @@ else
     OTP_ARG=""
 fi
 
-if [ $RUN_TOPGEN_FUSESOC == 1 ]; then
-    util/topgen-fusesoc.py --files-root=. --topname="$TOPLEVEL"
-    FILESET=topgen
-else
-    FILESET=top
-fi
-
 CORE_NAME="lowrisc:systems:chip_${FLAVOUR}_${TARGET}"
 
 fusesoc --verbose --cores-root=. \
-  run --flag=fileset_$FILESET --target=synth --setup --build \
+  run --target=synth --setup --build \
   --build-root="$OBJ_DIR/hw" \
   "$CORE_NAME" \
   --BootRomInitFile="$BOOTROM_VMEM" \

ci/scripts/build-chip-verilator.sh

@@ -18,20 +18,17 @@ tl="$1"
 
 case "$tl" in
     earlgrey)
-        fileset=fileset_top
         fusesoc_core=lowrisc:dv:chip_verilator_sim
         vname=Vchip_sim_tb
         verilator_options="--threads 4"
         make_options="-j 4"
         ;;
     englishbreakfast)
-        fileset=fileset_topgen
         fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
         vname=Vchip_englishbreakfast_verilator
         # Englishbreakfast on CI runs on a 2-core CPU
         verilator_options="--threads 2"
         make_options="-j 2"
-        util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast
         ;;
     *)
         echo >&2 "Unknown toplevel: $tl"
@@ -49,7 +46,7 @@ mkdir -p "$OBJ_DIR/hw"
 mkdir -p "$BIN_DIR/hw/top_${tl}"
 
 fusesoc --cores-root=. \
-  run --flag=$fileset --target=sim --setup --build \
+  run --target=sim --setup --build \
   --build-root="$OBJ_DIR/hw" \
   $fusesoc_core \
   --verilator_options="${verilator_options}" \

doc/getting_started/setup_fpga.md

@@ -132,7 +132,7 @@ The `--no-export` option of FuseSoC disables copying the source files into the s
 **Only create Vivado project directory by using FuseSoC directly (skipping Bazel invocation).**
 ```sh
 cd $REPO_TOP
-fusesoc --cores-root . run --flag=fileset_top --target=synth --no-export --setup lowrisc:systems:chip_earlgrey_${BOARD}
+fusesoc --cores-root . run --target=synth --no-export --setup lowrisc:systems:chip_earlgrey_${BOARD}
 ```
 
 You can then navigate to the created project directory, and open Vivado

hw/Makefile

@@ -46,7 +46,7 @@ IPS ?= aes           \
        uart          \
        usbdev
 
-TOPS ?= top_darjeeling top_earlgrey
+TOPS ?= top_darjeeling top_earlgrey top_englishbreakfast
 
 USE_BUFFER ?= 0
 

hw/top_englishbreakfast/README.md

@@ -0,0 +1,3 @@
+# Top Englishbreakfast
+
+This is an experimental top intended for SCA/FI activities.

hw/top_englishbreakfast/chip_englishbreakfast_cw305.core

@@ -10,9 +10,14 @@ filesets:
     depend:
       - lowrisc:prim_xilinx:prim_xilinx_default_pkg
       - lowrisc:systems:top_englishbreakfast:0.1
+      - lowrisc:systems:top_englishbreakfast_pkg
       - lowrisc:systems:top_earlgrey_ast
-      - lowrisc:systems:topgen
       - lowrisc:systems:top_earlgrey_padring
+      - lowrisc:systems:top_earlgrey_scan_role_pkg
+    files:
+      - rtl/clkgen_xil7series.sv
+      - rtl/usr_access_xil7series.sv
+      - rtl/autogen/chip_englishbreakfast_cw305.sv
     file_type: systemVerilogSource
 
   files_constraints:

hw/top_englishbreakfast/chip_englishbreakfast_verilator.core

@@ -8,7 +8,6 @@ filesets:
   files_sim_verilator:
     depend:
       - lowrisc:systems:top_englishbreakfast:0.1
-      - lowrisc:systems:topgen
       - lowrisc:dv_dpi_c:uartdpi
       - lowrisc:dv_dpi_sv:uartdpi
       - lowrisc:dv_dpi_c:gpiodpi

hw/top_englishbreakfast/data/autogen/BUILD

@@ -0,0 +1,10 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------#
+# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+# util/topgen.py -t hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+# -o hw/top_englishbreakfast
+
+exports_files(["top_englishbreakfast.gen.hjson"])

hw/top_englishbreakfast/data/autogen/defs.bzl

@@ -0,0 +1,55 @@
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# ------------------- W A R N I N G: A U T O - G E N E R A T E D   C O D E !! -------------------#
+# PLEASE DO NOT HAND-EDIT THIS FILE. IT HAS BEEN AUTO-GENERATED WITH THE FOLLOWING COMMAND:
+# util/topgen.py -t hw/top_englishbreakfast/data/top_englishbreakfast.hjson
+# -o hw/top_englishbreakfast
+
+load("//rules/opentitan:hw.bzl", "opentitan_top")
+load("//hw/ip/aes:defs.bzl", "AES")
+load("//hw/ip/aon_timer:defs.bzl", "AON_TIMER")
+load("//hw/top_englishbreakfast/ip/ast:defs.bzl", "AST")
+load("//hw/top_englishbreakfast/ip_autogen/clkmgr:defs.bzl", "CLKMGR")
+load("//hw/top_englishbreakfast/ip_autogen/flash_ctrl:defs.bzl", "FLASH_CTRL")
+load("//hw/ip/gpio:defs.bzl", "GPIO")
+load("//hw/top_englishbreakfast/ip_autogen/pinmux:defs.bzl", "PINMUX")
+load("//hw/top_englishbreakfast/ip_autogen/pwrmgr:defs.bzl", "PWRMGR")
+load("//hw/ip/rom_ctrl:defs.bzl", "ROM_CTRL")
+load("//hw/top_englishbreakfast/ip_autogen/rstmgr:defs.bzl", "RSTMGR")
+load("//hw/ip/rv_core_ibex:defs.bzl", "RV_CORE_IBEX")
+load("//hw/top_englishbreakfast/ip_autogen/rv_plic:defs.bzl", "RV_PLIC")
+load("//hw/ip/rv_timer:defs.bzl", "RV_TIMER")
+load("//hw/ip/spi_device:defs.bzl", "SPI_DEVICE")
+load("//hw/ip/spi_host:defs.bzl", "SPI_HOST")
+load("//hw/ip/sram_ctrl:defs.bzl", "SRAM_CTRL")
+load("//hw/ip/uart:defs.bzl", "UART")
+load("//hw/ip/usbdev:defs.bzl", "USBDEV")
+
+ENGLISHBREAKFAST = opentitan_top(
+    name = "englishbreakfast",
+    hjson = "//hw/top_englishbreakfast/data/autogen:top_englishbreakfast.gen.hjson",
+    top_lib = "//hw/top_englishbreakfast/sw/autogen:top_englishbreakfast",
+    top_ld = "//hw/top_englishbreakfast/sw/autogen:top_englishbreakfast_memory",
+    ips = [
+        AES,
+        AON_TIMER,
+        AST,
+        CLKMGR,
+        FLASH_CTRL,
+        GPIO,
+        PINMUX,
+        PWRMGR,
+        ROM_CTRL,
+        RSTMGR,
+        RV_CORE_IBEX,
+        RV_PLIC,
+        RV_TIMER,
+        SPI_DEVICE,
+        SPI_HOST,
+        SRAM_CTRL,
+        UART,
+        USBDEV,
+    ],
+)