[sram_ctrl,dv] Add cov exclusion for tlul_lc_gate

Excluding as we cannot reach the else condition in this module.
Detailed description is available in the .el file.

Signed-off-by: Pascal Nasahl <[email protected]>
Co-authored-by: Rupert Swarbrick <[email protected]>

hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el

@@ -23,6 +23,30 @@ Transition StFlush->StActive "76->289"
 Transition StFlush->StError "76->186"
 Transition StOutstanding->StFlush "231->76"
 
+// The following excludes the `if (outstanding_txn != '0)` condition in the `StErrorOutstanding`
+// state of the FSM inside the tlul_lc_gate module.
+//
+// There are two possible ways of entering the `StErrorOutstanding` state:
+// - (1) When the `lc_en_i` signal gets invalid, we follow `StActive -> StOutstanding -> StError`.
+//       We only can escape the `StError` state and enter `StErrorOutstanding` when the `lc_en_i`
+//       signal gets again valid.
+// - (2) The reset default state of this FSM is `StError`. When the `lc_en_i` signal gets valid, we
+//       enter the `StErrorOutstanding` state.
+//
+// (1) cannot happen in the `sram_ctrl module` as in this module `lc_en_i` is driven by the local
+// escalation register. Once we have escalated, we cannot set `lc_en_i` valid anymore.
+//
+// (2) happens as in the `sram_ctrl module` the `lc_en_i` is valid at reset. Hence, at reset, the
+// FSM immediately follows `StError` (cycle 0) -> `StErrorOutstanding` (cycle 1). To meet the
+// condition we are excluding here (i.e., `outstanding_txn` is nonzero), we would need no enqueue
+// a transaction in cycle 0. This would definitely be possible in the DV environment. However,
+// for Earl Grey this cannot happen as the only host that accesses the SRAM is Ibex. As the
+// boot address of Ibex points to the ROM and not the SRAM controller, a TL-UL request to the
+// SRAM in the first cycle cannot happen.
+CHECKSUM: "998580748 3219254590"
+INSTANCE: tb.dut.u_tlul_lc_gate
+Branch 2 "1850090820" "state_q" (12) "state_q StErrorOutstanding ,-,-,-,-,-,-,0"
+
 // The following exclusions were generated by UNR.
 CHECKSUM: "3523621980"
 ANNOTATION: "[UNR] all inputs are constant"