[sram_ctrl,dv] Add cov exclusion for tlul_lc_gate

Excluding as we cannot reach the else condition in this module.
Detailed description is available in the .el file.

Signed-off-by: Pascal Nasahl <[email protected]>
Signed-off-by: Rupert Swarbrick <[email protected]>

hw/ip/sram_ctrl/dv/cov/sram_ctrl_cov_excl.el

@@ -23,6 +23,21 @@ Transition StFlush->StActive "76->289"
 Transition StFlush->StError "76->186"
 Transition StOutstanding->StFlush "231->76"
 
+
+// The condition we are excluding here is when outstanding_txn is nonzero when passing through the
+// StErrorOutstanding state.
+//
+// For this to happen, we'd need to have an incomplete TL transaction pending (where the A side had
+// happened but not the D side) when the gate became enabled, caused by the lc_en_i becoming On.
+//
+// The FSM state comes out of reset as StError but the lc_en_i signal is On at reset in sram_ctrl,
+// so the FSM will follow the states StError (cycle 0), StErrorOutstanding (cycle 1), StActive
+// (cycle 2). It *is* theoretically possible for a transaction to be enqueued in cycle zero because
+// the TL inputs are top-level ports.
+CHECKSUM: "998580748 3219254590"
+INSTANCE: tb.dut.u_tlul_lc_gate
+Branch 2 "1850090820" "state_q" (12) "state_q StErrorOutstanding ,-,-,-,-,-,-,0"
+
 // The following exclusions were generated by UNR.
 CHECKSUM: "3523621980"
 ANNOTATION: "[UNR] all inputs are constant"