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[rom_ctrl, dv] Conditional coverage hole in tlul_adapter_sram fifos
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KinzaQamar committed Jan 9, 2025
1 parent 42a5979 commit 8106025
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34 changes: 34 additions & 0 deletions hw/ip/rom_ctrl/dv/cov/rom_ctrl_cov_excl.el
Original file line number Diff line number Diff line change
Expand Up @@ -146,6 +146,40 @@ Condition 37 "2164803938" "(tl_i_int.a_valid & reqfifo_wready & ((~error_interna
// u_sram_byte. But this makes req_o false and hence sram_ack false.
Condition 43 "2041272341" "(sram_ack & ((~we_o))) 1 -1" (2 "10")

// It is impossible to see !empty when under_rst.
//
// For under_rst=1, we are interested in rst_ni. If !rst_ni means under_rst=1 otherwise
// under_rst=0 if !under_rst else under_rst=0 on the next cycle of !rst_ni.
//
// empty is getting assigned by fifo_empty as Pass=0 for reqfifo. fifo_empty comes out as empty_o
// from u_fifo_cnt in u_reqfifo. empty_o=1 when wptr_wrap_cnt_o = rptr_wrapt_cnt_o in u_fifo_cnt.
// wptr_wrap_cnt_o and rptr_wrap_cnt_o comes out as cnt_o from u_wptr and u_rptr respectively. Both
// u_wptr and u_rptr are instances of same module (prim_count). Then cnt_o gets assigned by
// cnt_q[0] which is updated as a result of fpv_force[0] + cnt_unforced_q. fpv_force is wired to 0
// as rom_ctrl doesn't define the macro PrimCountFPV. cnt_unforced_q comes out as q_o from
// u_cnt_flop. In u_cnt_flop, q_o comes out from u_impl_generic instance which contains
// non-blocking assignments to q_o. If !rst_ni, then q_o will get assigned by a ResetValue which is
// 0 in this case. Otherwise, q_o will be delayed by d_i. This will get cnt_q=0 in both u_ptr and
// w_ptr which leads to cnt_o=0. When cnt_o in both w_ptr and r_ptr is 0 leads wptr_wrap_cnt_q and
// rptr_wrap_cnt_q to be equal. Which means the empty_o=1 in u_fifo_cnt and it will be seen as
// fifo_empty in u_reqfifo.
//
// To conclude the above discussion, when we are in reset we can't get the reqfifo full (or !empty).
// It can only happen when the adapter is out of reset and under_rst will be low on the next edge
// of clk. But q_o is delayed by d_i in u_impl_generic. So, during that entire cycle, q_o would
// have the reset value.
INSTANCE: tb.dut.u_tl_adapter_rom.u_reqfifo
Condition 2 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10")

// The reason for the next 2 conditional cases exclusions is same except Pass=1 for u_rspfifo. This
// means that empty is fifo_empty & ~wvalid_i. But there is no point to reason how to get !wvalid_i
// as fifo_empty would still be true when under_rst is true.
INSTANCE: tb.dut.u_tl_adapter_rom.u_rspfifo
Condition 2 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10")

INSTANCE: tb.dut.u_tl_adapter_rom.u_sramreqfifo
Condition 2 "1709501387" "(((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst))) 1 -1" (2 "10")

INSTANCE: tb.dut
// rom_cfg_i is tied to 0 inside the instantiation of rom_ctrl.
Toggle 0to1 rom_cfg_i.cfg [3:0] "logic rom_cfg_i.cfg[3:0]"
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