[englishbreakfast] Move to ordinary topgen flow

.gitignore

@@ -64,13 +64,6 @@ hw/foundry/
 # ROM_EXT signer vendored in dependencies
 sw/host/rom_ext_image_signer/vendored_dependencies
 
-# Autogen files for non-Earlgrey tops
-hw/top_englishbreakfast/**/autogen/
-hw/top_englishbreakfast/ip/alert_handler/dv/alert_handler_env_pkg__params.sv
-hw/top_englishbreakfast/ip/sensor_ctrl/rtl/*
-hw/top_englishbreakfast/ip/xbar_main/xbar_main.core
-hw/top_englishbreakfast/ip/xbar_peri/xbar_peri.core
-
 # Rust Cargo build system files.
 sw/host/**/target
 rust-project.json

BUILD.bazel

@@ -14,8 +14,6 @@ filegroup(
     name = "cores",
     srcs = [
         "check_tool_requirements.core",
-        "topgen.core",
-        "topgen-reg-only.core",
     ],
 )
 

ci/scripts/build-bitstream-vivado.sh

@@ -26,12 +26,10 @@ case x"$TOPLEVEL" in
     xtop_earlgrey)
         HAS_SCRAMBLED_ROM=1
         HAS_OTP=1
-        RUN_TOPGEN_FUSESOC=0
         ;;
     xtop_englishbreakfast)
         HAS_SCRAMBLED_ROM=0
         HAS_OTP=0
-        RUN_TOPGEN_FUSESOC=1
         ;;
     *)
         usage "Unknown toplevel: $TOPLEVEL"
@@ -86,17 +84,10 @@ else
     OTP_ARG=""
 fi
 
-if [ $RUN_TOPGEN_FUSESOC == 1 ]; then
-    util/topgen-fusesoc.py --files-root=. --topname="$TOPLEVEL"
-    FILESET=topgen
-else
-    FILESET=top
-fi
-
 CORE_NAME="lowrisc:systems:chip_${FLAVOUR}_${TARGET}"
 
 fusesoc --verbose --cores-root=. \
-  run --flag=fileset_$FILESET --target=synth --setup --build \
+  run --target=synth --setup --build \
   --build-root="$OBJ_DIR/hw" \
   "$CORE_NAME" \
   --BootRomInitFile="$BOOTROM_VMEM" \

ci/scripts/build-chip-verilator.sh

@@ -18,20 +18,17 @@ tl="$1"
 
 case "$tl" in
     earlgrey)
-        fileset=fileset_top
         fusesoc_core=lowrisc:dv:chip_verilator_sim
         vname=Vchip_sim_tb
         verilator_options="--threads 4"
         make_options="-j 4"
         ;;
     englishbreakfast)
-        fileset=fileset_topgen
         fusesoc_core=lowrisc:systems:chip_englishbreakfast_verilator
         vname=Vchip_englishbreakfast_verilator
         # Englishbreakfast on CI runs on a 2-core CPU
         verilator_options="--threads 2"
         make_options="-j 2"
-        util/topgen-fusesoc.py --files-root=. --topname=top_englishbreakfast
         ;;
     *)
         echo >&2 "Unknown toplevel: $tl"
@@ -49,7 +46,7 @@ mkdir -p "$OBJ_DIR/hw"
 mkdir -p "$BIN_DIR/hw/top_${tl}"
 
 fusesoc --cores-root=. \
-  run --flag=$fileset --target=sim --setup --build \
+  run --target=sim --setup --build \
   --build-root="$OBJ_DIR/hw" \
   $fusesoc_core \
   --verilator_options="${verilator_options}" \

doc/getting_started/setup_fpga.md

@@ -132,7 +132,7 @@ The `--no-export` option of FuseSoC disables copying the source files into the s
 **Only create Vivado project directory by using FuseSoC directly (skipping Bazel invocation).**
 ```sh
 cd $REPO_TOP
-fusesoc --cores-root . run --flag=fileset_top --target=synth --no-export --setup lowrisc:systems:chip_earlgrey_${BOARD}
+fusesoc --cores-root . run --target=synth --no-export --setup lowrisc:systems:chip_earlgrey_${BOARD}
 ```
 
 You can then navigate to the created project directory, and open Vivado

hw/Makefile

@@ -46,7 +46,7 @@ IPS ?= aes           \
        uart          \
        usbdev
 
-TOPS ?= top_darjeeling top_earlgrey
+TOPS ?= top_darjeeling top_earlgrey top_englishbreakfast
 
 USE_BUFFER ?= 0