Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Option to factor out "clk" from "spi_flash" on Lattice ECP5 #38

Open
wants to merge 4 commits into
base: master
Choose a base branch
from
Open

Option to factor out "clk" from "spi_flash" on Lattice ECP5 #38

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
4 commits
Select commit Hold shift + click to select a range
720717b
versa_ecp5: Allow replacing SPI flash clock with user clock
HarryMakes Nov 28, 2019
82f8a56
versa_ecp5: Fix swapped miso/mosi balls under master SPI mode
HarryMakes Dec 11, 2019
d51e1d5
versa_ecp5: Fix tx_ctl & rx_ctl misspelling on eth_rgmii
HarryMakes Jan 21, 2020
0af812c
versa_ecp5: Detects clk=None for using USRMCLK
Apr 23, 2020
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 4 additions & 1 deletion nmigen_boards/resources/memory.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,10 @@ def SPIFlashResources(*args, cs, clk, mosi, miso, wp=None, hold=None,
if attrs is not None:
io_all.append(attrs)
io_all.append(Subsignal("cs", PinsN(cs, dir="o", conn=conn)))
io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))
# Only append a Subsignal if no user clock is to be used as the SPI clock
# The user of user clock is indicated by `clk="user_clk"`
if clk is not None:
io_all.append(Subsignal("clk", Pins(clk, dir="o", conn=conn, assert_width=1)))

io_1x = list(io_all)
io_1x.append(Subsignal("mosi", Pins(mosi, dir="o", conn=conn, assert_width=1)))
Expand Down
40 changes: 30 additions & 10 deletions nmigen_boards/versa_ecp5.py
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -6,16 +6,16 @@
from .resources import *


__all__ = ["VersaECP5Platform"]
__all__ = ["VersaECP5Platform", "VersaECP5Platform_USRMCLK"]


class VersaECP5Platform(LatticeECP5Platform):
class _VersaECP5PlatformBase(LatticeECP5Platform):
device = "LFE5UM-45F"
package = "BG381"
speed = "8"
default_clk = "clk100"
default_rst = "rst"
resources = [
_resources = [
Resource("rst", 0, PinsN("T1", dir="i"), Attrs(IO_TYPE="LVCMOS33")),
Resource("clk100", 0, DiffPairs("P3", "P4", dir="i"),
Clock(100e6), Attrs(IO_TYPE="LVDS")),
Expand Down Expand Up @@ -54,11 +54,6 @@ class VersaECP5Platform(LatticeECP5Platform):
attrs=Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")
),

*SPIFlashResources(0,
cs="R2", clk="U3", miso="W2", mosi="V2", wp="Y2", hold="W1",
attrs=Attrs(IO_STANDARD="LVCMOS33")
),

Resource("eth_clk125", 0, Pins("L19", dir="i"),
Clock(125e6), Attrs(IO_TYPE="LVCMOS25")),
Resource("eth_clk125_pll", 0, Pins("U16", dir="i"),
Expand Down Expand Up @@ -92,10 +87,10 @@ class VersaECP5Platform(LatticeECP5Platform):
Subsignal("mdc", Pins("G19", dir="o")),
Subsignal("mdio", Pins("H20", dir="io")),
Subsignal("tx_clk", Pins("C20", dir="o")),
Subsignal("tx_ctrl", Pins("E19", dir="o")),
Subsignal("tx_ctl", Pins("E19", dir="o")),
Subsignal("tx_data", Pins("J17 J16 D19 D20", dir="o")),
Subsignal("rx_clk", Pins("J19", dir="i")),
Subsignal("rx_ctrl", Pins("F19", dir="i")),
Subsignal("rx_ctl", Pins("F19", dir="i")),
Subsignal("rx_data", Pins("G18 G16 H18 H17", dir="i")),
Attrs(IO_TYPE="LVCMOS25")
),
Expand Down Expand Up @@ -171,6 +166,31 @@ def toolchain_program(self, products, name):
])


class VersaECP5Platform(_VersaECP5PlatformBase):
resources = (
_VersaECP5PlatformBase._resources +
[
*SPIFlashResources(0,
cs="R2", clk="U3", miso="V2", mosi="W2", wp="Y2", hold="W1",
attrs=Attrs(IO_STANDARD="LVCMOS33")
)
]
)


class VersaECP5Platform_USRMCLK(_VersaECP5PlatformBase):
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Probably better to add a parameter to __init__ instead of having two separate classes. This is what we did in other places (e.g. Migen), having one class for each combination of options does not scale.

resources = (
_VersaECP5PlatformBase._resources +
[
# Note: after requesting from this platform, user should assign its clk
*SPIFlashResources(0,
cs="R2", clk=None, miso="V2", mosi="W2", wp="Y2", hold="W1",
attrs=Attrs(IO_STANDARD="LVCMOS33")
)
]
)


if __name__ == "__main__":
from .test.blinky import *
VersaECP5Platform().build(Blinky(), do_program=True)