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added parameters to some components, and added subcircuit param test
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hb020 committed Oct 12, 2024
1 parent 2fbdd73 commit 8461f0f
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Showing 7 changed files with 17 additions and 13 deletions.
15 changes: 5 additions & 10 deletions spicelib/editor/spice_editor.py
Original file line number Diff line number Diff line change
Expand Up @@ -76,16 +76,11 @@ def VALUE_RGX(number_regex):
# This implementation replaces everything after the 2 first nets
'J': r"^(?P<designator>J§?\w+)(?P<nodes>(\s+\S+){3})\s+(?P<value>\w+)" +
PARAM_RGX + ".*?$", # JFET
'K': r"^(?P<designator>K§?\w+)(?P<nodes>(\s+\S+){2,4})\s+(?P<value>[\+\-]?[0-9\.E+-]+[kmuµnpgt]?).*$",
# Mutual Inductance
'L': r"^(?P<designator>L§?\w+)(?P<nodes>(\s+\S+){2})\s+(?P<value>({)?(?(5).*}|([0-9\.E+-]+(Meg|[kmuµnpgt])?H?))).*$",
# Inductance
'M': r"^(?P<designator>M§?\w+)(?P<nodes>(\s+\S+){3,4})\s+(?P<value>\w+).*$",
# MOSFET TODO: Parameters substitution not supported
'O': r"^(?P<designator>O§?\w+)(?P<nodes>(\s+\S+){4})\s+(?P<value>\w+).*$",
# Lossy Transmission Line TODO: Parameters substitution not supported
'Q': r"^(?P<designator>Q§?\w+)(?P<nodes>(\s+\S+){3,4})\s+(?P<value>\w+)" + PARAM_RGX + ".*?$",
# Bipolar TODO: Parameters substitution not supported
'K': r"^(?P<designator>K§?\w+)(?P<nodes>(\s+\S+){2,4})\s+(?P<value>[\+\-]?[0-9\.E+-]+[kmuµnpgt]?).*$", # Mutual Inductance
'L': r"^(?P<designator>L§?\w+)(?P<nodes>(\s+\S+){2})\s+(?P<value>({)?(?(5).*}|([0-9\.E+-]+(Meg|[kmuµnpgt])?H?))).*$", # Inductance
'M': r"^(?P<designator>M§?\w+)(?P<nodes>(\s+\S+){3,4})\s+(?P<value>\w+)" + PARAM_RGX + ".*?$", # MOSFET
'O': r"^(?P<designator>O§?\w+)(?P<nodes>(\s+\S+){4})\s+(?P<value>\w+)" + PARAM_RGX + ".*?$", # Lossy Transmission Line
'Q': r"^(?P<designator>Q§?\w+)(?P<nodes>(\s+\S+){3,4})\s+(?P<value>\w+)" + PARAM_RGX + ".*?$", # Bipolar
'R': r"^(?P<designator>R§?\w+)(?P<nodes>(\s+\S+){2})(?P<model>\s+\w+)?\s+" +
"(R=)?" + VALUE_RGX(FLOAT_RGX + r"(Meg|[kRmuµnpfgt])?\d*") +
PARAM_RGX + ".*?$", # Resistor
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1 change: 1 addition & 0 deletions unittests/golden/subcircuit_edit.asc
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Expand Up @@ -11,6 +11,7 @@ FLAG 288 144 OUT
SYMBOL cap 176 144 R0
SYMATTR InstName C1
SYMATTR Value 22n
SYMATTR SpiceLine Rser=1
SYMBOL cap -64 144 R0
SYMATTR InstName C2
SYMATTR Value 1n
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2 changes: 1 addition & 1 deletion unittests/golden/top_circuit_edit.net
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Expand Up @@ -28,7 +28,7 @@ C3 C B 100n
.backanno
***** SpiceEditor Manipulated this sub-circuit ****
.subckt sub_circuit_XX1 IN OUT
C1 OUT 0 22n
C1 OUT 0 22n Rser=1
X2 IN 0 snubber
L1 IN OUT 4uH
.ENDS sub_circuit_XX1
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2 changes: 1 addition & 1 deletion unittests/golden/top_circuit_edit1.net
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ C3 C B 100n
.backanno
***** SpiceEditor Manipulated this sub-circuit ****
.subckt sub_circuit_XX1 IN OUT
C1 OUT 0 22n
C1 OUT 0 22n Rser=1
X2 IN 0 snubber_X2
L1 IN OUT 4uH
***** SpiceEditor Manipulated this sub-circuit ****
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2 changes: 1 addition & 1 deletion unittests/golden/top_circuit_edit2.net
Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ C3 C B 100n
.backanno
***** SpiceEditor Manipulated this sub-circuit ****
.subckt sub_circuit_XX1 IN OUT
C1 OUT 0 22n
C1 OUT 0 22n Rser=1
X2 IN 0 snubber_X2
L1 IN OUT 4uH
***** SpiceEditor Manipulated this sub-circuit ****
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4 changes: 4 additions & 0 deletions unittests/test_asc_editor.py
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Expand Up @@ -158,6 +158,10 @@ def test_subcircuits_edit(self):
test_add_parameter=34.45, )
# END identical part with test_spice_editor.py:test_subcircuits_edit()

# Set component parameter
my_edt.get_subcircuit(sc).set_component_parameters("C1", Rser=1) # set string value via indirect method
self.assertEqual(my_edt.get_subcircuit(sc).get_component_parameters("C1"), {'Value': '22n', 'SpiceLine': 'Rser=1', 'Rser': 1}, "Subcircuit parameters for X1:C1")

S = my_edt.get_subcircuit(sc)
S.asc_file_path = temp_dir + "subcircuit_edit.asc" # Only for test purposes
my_edt.save_netlist(temp_dir + "top_circuit_edit.asc")
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4 changes: 4 additions & 0 deletions unittests/test_spice_editor.py
Original file line number Diff line number Diff line change
Expand Up @@ -305,6 +305,10 @@ def test_subcircuits_edit(self):
test_add_parameter=34.45, )
# END identical part with test_asc_editor.py:test_subcircuits_edit()

# Set component parameter
my_edt.get_subcircuit(sc).set_component_parameters("C1", Rser=1) # set string value via indirect method
self.assertEqual(my_edt.get_subcircuit(sc).get_component_parameters("C1"), {"Rser": 1}, "Subcircuit parameters for X1:C1")

my_edt.save_netlist(temp_dir + "top_circuit_edit.net")
self.equalFiles(temp_dir + "top_circuit_edit.net", golden_dir + "top_circuit_edit.net")

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