Added new models

BUFGMUX.v

@@ -0,0 +1,75 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/BUFGMUX.v,v 1.16 2009/08/21 23:55:43 harikr Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Global Clock Mux Buffer with Output State 0
+// /___/   /\     Filename : BUFGMUX.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:42:14 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+//    05/23/07 - Changed timescale to 1 ps / 1 ps.
+//    01/11/08 - Add CLK_SEL_TYPE attribute.
+// End Revision
+
+`timescale  1 ps / 1 ps
+
+module BUFGMUX (O, I0, I1, S);
+
+    parameter CLK_SEL_TYPE = "SYNC";
+    output O;
+    input  I0, I1, S;
+
+    reg q0, q1;
+    reg q0_enable, q1_enable;
+    wire q0_t, q1_t;
+    reg clk_sel_in;
+
+    tri0 GSR = glbl.GSR;
+
+    bufif1 B0 (O, I0, q0_t);
+    bufif1 B1 (O, I1, q1_t);
+    pulldown P1 (O);
+
+    initial
+       clk_sel_in = (CLK_SEL_TYPE == "ASYNC") ? 1 : 0;
+
+       assign q0_t = (clk_sel_in) ? ~S : q0;
+       assign q1_t = (clk_sel_in) ? S : q1;
+
+	always @(GSR or I0 or S or q0_enable)
+ 	    if (GSR)
+		q0 <= 1;
+ 	    else if (!I0)
+		q0 <= !S && q0_enable;
+
+	always @(GSR or I1 or S or q1_enable)
+ 	    if (GSR)
+		q1 <= 0;
+ 	    else if (!I1)
+		q1 <= S && q1_enable;
+
+	always @(GSR or q1 or I0)
+ 	    if (GSR)
+		q0_enable <= 1;
+	    else if (q1)
+		q0_enable <= 0;
+	    else if (I0)
+		q0_enable <= !q1;
+
+	always @(GSR or q0 or I1)
+ 	    if (GSR)
+		q1_enable <= 0;
+	    else if (q0)
+		q1_enable <= 0;
+	    else if (I1)
+		q1_enable <= !q0;
+
+endmodule

BUFPLL.v

@@ -0,0 +1,71 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/stan/BUFPLL.v,v 1.11 2012/10/04 22:10:38 robh Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2007 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Phase Locked Loop buffer for Spartan Series
+// /___/   /\     Filename : BUFPLL.v
+// \   \  /  \
+//  \___\/\___\
+//
+///////////////////////////////////////////////////////////////////////////////
+// Revision:
+//    06/09/08 - Initial version.
+//    08/19/08 - IR 479918 -- added 100 ps latency to sequential paths.
+//    02/10/09 - IR 505709 -- correlate SERDESSTROBE to GLCK
+//    03/24/09 - CR 514119 -- sync output to LOCKED high signal 
+//    06/16/09 - CR 525221 -- added ENABLE_SYNC attribute
+//    02/08/11 - CR 584404 -- restart, if LOCK lost or reprogrammed
+//    01/11/12 - CR 639574 -- aligned the SERDESTROBE to GCLK when ENABLE_SYNC=TRUE
+//    10/04/12 - 680268 -- aligned the SERDESTROBE to IOCLK always and other clean up
+// End Revision
+///////////////////////////////////////////////////////////////////////////////
+
+`timescale  1 ps / 1 ps
+
+module BUFPLL (IOCLK, LOCK, SERDESSTROBE, GCLK, LOCKED, PLLIN);
+
+
+    parameter integer DIVIDE = 1;        // {1..8}
+    parameter ENABLE_SYNC = "TRUE";
+
+
+
+    output IOCLK;
+    output LOCK;
+    output SERDESSTROBE;
+
+    input GCLK;
+    input LOCKED;
+    input PLLIN;
+
+
+   assign IOCLK = PLLIN;
+   assign LOCK = LOCKED;
+
+   reg [3:0] div_count;
+   reg 	     serdes_strobe;
+   wire [3:0] next_div_count = div_count + 1;
+
+   /* verilator lint_off WIDTH */
+   wire [3:0] divider = DIVIDE;
+
+   always @(posedge IOCLK) begin
+      if(next_div_count == divider) begin
+	 serdes_strobe <= 1;
+	 div_count <= 0;
+      end else begin
+	 serdes_strobe <= 0;
+	 div_count <= next_div_count;
+      end
+   end
+   assign SERDESSTROBE = (DIVIDE == 1) ? 1'b0 : serdes_strobe;
+   /* verilator lint_on WIDTH */
+
+endmodule // BUFPLL
+