error if not verilator.

oliverbunting · Sep 25, 2015 · 1ac36f2 · 1ac36f2
1 parent 884082f
commit 1ac36f2
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/DCM_SP.v b/DCM_SP.v
@@ -79,6 +79,8 @@ endgenerate
 
   assign LOCKED = lock_2x && lock_fx;
 
+`else
+ $error ("Unimplemented DCM_SP for non verilator sim.  Should use original Xilinx sim libs not this library." );
 `endif
 
 endmodule