improved iserdes2, but still is not correct

ISERDES2.v

@@ -63,11 +63,23 @@ module ISERDES2 (
   assign DFB = 0;
   assign FABRICOUT = 0;
   assign INCDEC = 0;
-  assign Q1 = 0;
-  assign Q2 = 0;
-  assign Q3 = 0;
-  assign Q4 = 0;
+//  assign Q1 = 0;
+//  assign Q2 = 0;
+//  assign Q3 = 0;
+//  assign Q4 = 0;
   assign SHIFTOUT = 0;
   assign VALID = 0;
 
+   reg [3:0] srA;
+   wire      Din = (SERDES_MODE == "SLAVE") ? SHIFTIN : D;
+
+   always @(posedge CLK0 or posedge CLK1) begin
+      srA <= { Din, srA[2:0] };
+   end
+   assign Q1 = srA[0];
+   assign Q2 = srA[1];
+   assign Q3 = srA[2];
+   assign Q4 = srA[3];
+
+
 endmodule // ISERDES2