Floating-point wrappers in the STL

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With wrappers for builtin floating-point modules (On Intel & Xilinx FPGAs), we have a far more competent language to be used at PC2.

Full parametrizability will likely be blocked by #25, but basic 32-bit floats shouldn't be an issue

• Investigate such floating point libraries for Xilinx FPGAs (Vivado)
• Investigate for Intel FPGAs (Intel Quartus)
• Make shared library, with interface that is compatible with both

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http://www.flopoco.org/ is a good resource for this

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As is https://www.sollya.org/

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Of course, DSP-based floating point units will be provided by Intel and Xilinx specifically. Look through documentation to see what's possible. Maybe look at HLS generated hardware?

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More https://github.com/freecores/fpu_double

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So I saw another project, from my competitor Spade. They're wrapping Berkley-Hardfloat. maybe worth looking into?
https://github.com/ethanuppal/hardfloat-spade

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Repository created: https://github.com/pc2/sus-float