Skip to content

Commit

Permalink
Merge pull request cc65#2438 from ops/exehdr
Browse files Browse the repository at this point in the history
Add missing EXEHDR
  • Loading branch information
mrdudz authored May 15, 2024
2 parents 90723d7 + 074ec82 commit 84153e8
Show file tree
Hide file tree
Showing 3 changed files with 3 additions and 0 deletions.
1 change: 1 addition & 0 deletions cfg/vic20-asm-32k.cfg
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ MEMORY {
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, optional = yes;
LOADADDR: load = LOADADDR, type = ro;
EXEHDR: load = MAIN, type = ro, optional = yes;
CODE: load = MAIN, type = ro;
RODATA: load = MAIN, type = ro;
DATA: load = MAIN, type = rw;
Expand Down
1 change: 1 addition & 0 deletions cfg/vic20-asm-3k.cfg
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ MEMORY {
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, optional = yes;
LOADADDR: load = LOADADDR, type = ro;
EXEHDR: load = MAIN, type = ro, optional = yes;
CODE: load = MAIN, type = ro;
RODATA: load = MAIN, type = ro;
DATA: load = MAIN, type = rw;
Expand Down
1 change: 1 addition & 0 deletions cfg/vic20-asm.cfg
Original file line number Diff line number Diff line change
Expand Up @@ -14,6 +14,7 @@ MEMORY {
SEGMENTS {
ZEROPAGE: load = ZP, type = zp, optional = yes;
LOADADDR: load = LOADADDR, type = ro;
EXEHDR: load = MAIN, type = ro, optional = yes;
CODE: load = MAIN, type = ro;
RODATA: load = MAIN, type = ro;
DATA: load = MAIN, type = rw;
Expand Down

0 comments on commit 84153e8

Please sign in to comment.