update supported ruby version

(refs: rggen/rggen#226)
rggen · Dec 30, 2024 · 0738422 · 0738422
1 parent 58bba68
commit 0738422
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Showing 21 changed files with 51 additions and 51 deletions.
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -8,7 +8,7 @@ jobs:
 
     strategy:
       matrix:
-        ruby: ['3.3', '3.2', '3.1', '3.0']
+        ruby: ['3.4', '3.3', '3.2', '3.1']
         frozen_string_literal: ['yes', 'no']
 
     env:

diff --git a/lib/rggen/verilog/rtl/bit_field/type/custom.rb b/lib/rggen/verilog/rtl/bit_field/type/custom.rb
@@ -5,39 +5,39 @@
     build do
       if external_read_data?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       else
         output :value_out, {
-          name: "o_#{full_name}", width: width, array_size: array_size
+          name: "o_#{full_name}", width:, array_size:
         }
       end
       if bit_field.hw_write?
         input :hw_write_enable, {
-          name: "i_#{full_name}_hw_write_enable", width: 1, array_size: array_size
+          name: "i_#{full_name}_hw_write_enable", width: 1, array_size:
         }
         input :hw_write_data, {
-          name: "i_#{full_name}_hw_write_data", width: width, array_size: array_size
+          name: "i_#{full_name}_hw_write_data", width:, array_size:
         }
       end
       if bit_field.hw_set?
         input :hw_set, {
-          name: "i_#{full_name}_hw_set", width: width, array_size: array_size
+          name: "i_#{full_name}_hw_set", width:, array_size:
         }
       end
       if bit_field.hw_clear?
         input :hw_clear, {
-          name: "i_#{full_name}_hw_clear", width: width, array_size: array_size
+          name: "i_#{full_name}_hw_clear", width:, array_size:
         }
       end
       if bit_field.write_trigger?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
       if bit_field.read_trigger?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb b/lib/rggen/verilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb
@@ -4,14 +4,14 @@
   verilog_rtl do
     build do
       input :set, {
-        name: "i_#{full_name}_set", width: width, array_size: array_size
+        name: "i_#{full_name}_set", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if bit_field.reference?
         output :value_unmasked, {
-          name: "o_#{full_name}_unmasked", width: width, array_size: array_size
+          name: "o_#{full_name}_unmasked", width:, array_size:
         }
       end
     end

diff --git a/lib/rggen/verilog/rtl/bit_field/type/ro_rotrg.rb b/lib/rggen/verilog/rtl/bit_field/type/ro_rotrg.rb
@@ -5,12 +5,12 @@
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rotrg?
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/verilog/rtl/bit_field/type/rohw.rb b/lib/rggen/verilog/rtl/bit_field/type/rohw.rb
@@ -5,14 +5,14 @@
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid", width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.rb b/lib/rggen/verilog/rtl/bit_field/type/row0trg_row1trg.rb
@@ -5,11 +5,11 @@
     build do
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/rowo_rowotrg.rb b/lib/rggen/verilog/rtl/bit_field/type/rowo_rowotrg.rb
@@ -4,19 +4,19 @@
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       unless bit_field.reference?
         input :value_in, {
-          name: "i_#{full_name}", width: width, array_size: array_size
+          name: "i_#{full_name}", width:, array_size:
         }
       end
       if rowotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb b/lib/rggen/verilog/rtl/bit_field/type/rs_w0s_w1s_ws_wos.rb
@@ -4,10 +4,10 @@
   verilog_rtl do
     build do
       input :clear, {
-        name: "i_#{full_name}_clear", width: width, array_size: array_size
+        name: "i_#{full_name}_clear", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/rw_rwtrg_w1.rb b/lib/rggen/verilog/rtl/bit_field/type/rw_rwtrg_w1.rb
@@ -4,14 +4,14 @@
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if rwtrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
         output :read_trigger, {
-          name: "o_#{full_name}_read_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_read_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/verilog/rtl/bit_field/type/rwc.rb b/lib/rggen/verilog/rtl/bit_field/type/rwc.rb
@@ -5,11 +5,11 @@
     build do
       unless bit_field.reference?
         input :clear, {
-          name: "i_#{full_name}_clear", width: 1, array_size: array_size
+          name: "i_#{full_name}_clear", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.rb b/lib/rggen/verilog/rtl/bit_field/type/rwe_rwl.rb
@@ -6,11 +6,11 @@
       unless bit_field.reference?
         input :control, {
           name: "i_#{full_name}_#{enable_or_lock}",
-          width: 1, array_size: array_size
+          width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/rwhw.rb b/lib/rggen/verilog/rtl/bit_field/type/rwhw.rb
@@ -5,14 +5,14 @@
     build do
       unless bit_field.reference?
         input :valid, {
-          name: "i_#{full_name}_valid", width: 1, array_size: array_size
+          name: "i_#{full_name}_valid", width: 1, array_size:
         }
       end
       input :value_in, {
-        name: "i_#{full_name}", width: width, array_size: array_size
+        name: "i_#{full_name}", width:, array_size:
       }
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/rws.rb b/lib/rggen/verilog/rtl/bit_field/type/rws.rb
@@ -5,11 +5,11 @@
     build do
       unless bit_field.reference?
         input :set, {
-          name: "i_#{full_name}_set", width: 1, array_size: array_size
+          name: "i_#{full_name}_set", width: 1, array_size:
         }
       end
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb b/lib/rggen/verilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb
@@ -6,7 +6,7 @@
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/w0t_w1t.rb b/lib/rggen/verilog/rtl/bit_field/type/w0t_w1t.rb
@@ -4,7 +4,7 @@
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/w0trg_w1trg.rb b/lib/rggen/verilog/rtl/bit_field/type/w0trg_w1trg.rb
@@ -4,7 +4,7 @@
   verilog_rtl do
     build do
       output :trigger, {
-        name: "o_#{full_name}_trigger", width: width, array_size: array_size
+        name: "o_#{full_name}_trigger", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/bit_field/type/wo_wo1_wotrg.rb b/lib/rggen/verilog/rtl/bit_field/type/wo_wo1_wotrg.rb
@@ -4,11 +4,11 @@
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
       if wotrg?
         output :write_trigger, {
-          name: "o_#{full_name}_write_trigger", width: 1, array_size: array_size
+          name: "o_#{full_name}_write_trigger", width: 1, array_size:
         }
       end
     end

diff --git a/lib/rggen/verilog/rtl/bit_field/type/wrc_wrs.rb b/lib/rggen/verilog/rtl/bit_field/type/wrc_wrs.rb
@@ -4,7 +4,7 @@
   verilog_rtl do
     build do
       output :value_out, {
-        name: "o_#{full_name}", width: width, array_size: array_size
+        name: "o_#{full_name}", width:, array_size:
       }
     end
 

diff --git a/lib/rggen/verilog/rtl/feature.rb b/lib/rggen/verilog/rtl/feature.rb
@@ -8,20 +8,20 @@ class Feature < SystemVerilog::RTL::Feature
 
         private
 
-        def create_variable(data_type, attributes, &block)
+        def create_variable(data_type, attributes, &)
           attributes = attributes.merge(array_format: :serialized)
           super
         end
 
-        def create_port(direction, attributes, &block)
+        def create_port(direction, attributes, &)
           attributes =
             attributes
               .except(:data_type)
-              .merge(direction: direction, array_format: :serialized)
-          DataObject.new(:argument, attributes, &block)
+              .merge(direction:, array_format: :serialized)
+          DataObject.new(:argument, attributes, &)
         end
 
-        def create_parameter(parameter_type, attributes, &block)
+        def create_parameter(parameter_type, attributes, &)
           attributes = attributes.merge(array_format: :serialized)
           super
         end

diff --git a/lib/rggen/verilog/utility.rb b/lib/rggen/verilog/utility.rb
@@ -5,8 +5,8 @@ module Verilog
     module Utility
       private
 
-      def local_scope(name, attributes = {}, &block)
-        LocalScope.new(attributes.merge(name: name), &block).to_code
+      def local_scope(name, attributes = {}, &)
+        LocalScope.new(attributes.merge(name:), &).to_code
       end
 
       def fill_0(width)

diff --git a/rggen-verilog.gemspec b/rggen-verilog.gemspec
@@ -25,7 +25,7 @@ Gem::Specification.new do |spec|
     `git ls-files lib LICENSE CODE_OF_CONDUCT.md README.md`.split($RS)
   spec.require_paths = ['lib']
 
-  spec.required_ruby_version = Gem::Requirement.new('>= 3.0')
+  spec.required_ruby_version = Gem::Requirement.new('>= 3.1')
 
   spec.add_runtime_dependency 'rggen-systemverilog', '>= 0.33.1'
 end