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shader_recompiler: BUFFER_ATOMIC_SWAP Opcode #566

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merged 4 commits into from
Aug 26, 2024
Merged

shader_recompiler: BUFFER_ATOMIC_SWAP Opcode #566

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824d1dd
shader_recompiler: BUFFER_ATOMIC_SWAP Opcode
lzardy Aug 24, 2024
1d5cf78
clang
lzardy Aug 24, 2024
4b054b3
Merge remote-tracking branch 'upstream/main'
lzardy Aug 25, 2024
d142708
follow 32 convention
lzardy Aug 26, 2024
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2 changes: 1 addition & 1 deletion src/shader_recompiler/backend/spirv/emit_spirv_atomic.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -102,7 +102,7 @@ Id EmitBufferAtomicXor32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addres
return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicXor);
}

Id EmitBufferAtomicExchange32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
Id EmitBufferAtomicSwap32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value) {
return BufferAtomicU32(ctx, inst, handle, address, value, &Sirit::Module::OpAtomicExchange);
}

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2 changes: 1 addition & 1 deletion src/shader_recompiler/backend/spirv/emit_spirv_instructions.h
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Expand Up @@ -91,7 +91,7 @@ Id EmitBufferAtomicDec32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id addres
Id EmitBufferAtomicAnd32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicOr32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicXor32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicExchange32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitBufferAtomicSwap32(EmitContext& ctx, IR::Inst* inst, u32 handle, Id address, Id value);
Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, u32 comp);
Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, u32 comp);
void EmitSetAttribute(EmitContext& ctx, IR::Attribute attr, Id value, u32 comp);
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4 changes: 3 additions & 1 deletion src/shader_recompiler/frontend/translate/vector_memory.cpp
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Expand Up @@ -109,6 +109,8 @@ void Translator::EmitVectorMemory(const GcnInst& inst) {
// Buffer atomic operations
case Opcode::BUFFER_ATOMIC_ADD:
return BUFFER_ATOMIC(AtomicOp::Add, inst);
case Opcode::BUFFER_ATOMIC_SWAP:
return BUFFER_ATOMIC(AtomicOp::Swap, inst);
default:
LogMissingOpcode(inst);
}
Expand Down Expand Up @@ -474,7 +476,7 @@ void Translator::BUFFER_ATOMIC(AtomicOp op, const GcnInst& inst) {
const IR::Value original_val = [&] {
switch (op) {
case AtomicOp::Swap:
return ir.BufferAtomicExchange(handle, address, vdata_val, info);
return ir.BufferAtomicSwap(handle, address, vdata_val, info);
case AtomicOp::Add:
return ir.BufferAtomicIAdd(handle, address, vdata_val, info);
case AtomicOp::Smin:
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6 changes: 3 additions & 3 deletions src/shader_recompiler/ir/ir_emitter.cpp
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Expand Up @@ -404,9 +404,9 @@ Value IREmitter::BufferAtomicXor(const Value& handle, const Value& address, cons
return Inst(Opcode::BufferAtomicXor32, Flags{info}, handle, address, value);
}

Value IREmitter::BufferAtomicExchange(const Value& handle, const Value& address, const Value& value,
BufferInstInfo info) {
return Inst(Opcode::BufferAtomicExchange32, Flags{info}, handle, address, value);
Value IREmitter::BufferAtomicSwap(const Value& handle, const Value& address, const Value& value,
BufferInstInfo info) {
return Inst(Opcode::BufferAtomicSwap32, Flags{info}, handle, address, value);
}

void IREmitter::StoreBufferFormat(int num_dwords, const Value& handle, const Value& address,
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4 changes: 2 additions & 2 deletions src/shader_recompiler/ir/ir_emitter.h
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Expand Up @@ -115,8 +115,8 @@ class IREmitter {
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicXor(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicExchange(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);
[[nodiscard]] Value BufferAtomicSwap(const Value& handle, const Value& address,
const Value& value, BufferInstInfo info);

[[nodiscard]] U32 LaneId();
[[nodiscard]] U32 WarpId();
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2 changes: 1 addition & 1 deletion src/shader_recompiler/ir/microinstruction.cpp
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Expand Up @@ -70,7 +70,7 @@ bool Inst::MayHaveSideEffects() const noexcept {
case Opcode::BufferAtomicAnd32:
case Opcode::BufferAtomicOr32:
case Opcode::BufferAtomicXor32:
case Opcode::BufferAtomicExchange32:
case Opcode::BufferAtomicSwap32:
case Opcode::WriteSharedU128:
case Opcode::WriteSharedU64:
case Opcode::WriteSharedU32:
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4 changes: 2 additions & 2 deletions src/shader_recompiler/ir/opcodes.inc
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Expand Up @@ -95,7 +95,7 @@ OPCODE(StoreBufferFormatF32x4, Void, Opaq
OPCODE(StoreBufferU32, Void, Opaque, Opaque, U32, )

// Buffer atomic operations
OPCODE(BufferAtomicIAdd32, U32, Opaque, Opaque, U32 )
OPCODE(BufferAtomicIAdd32, U32, Opaque, Opaque, U32 )
OPCODE(BufferAtomicSMin32, U32, Opaque, Opaque, U32 )
OPCODE(BufferAtomicUMin32, U32, Opaque, Opaque, U32 )
OPCODE(BufferAtomicSMax32, U32, Opaque, Opaque, U32 )
Expand All @@ -105,7 +105,7 @@ OPCODE(BufferAtomicDec32, U32, Opaq
OPCODE(BufferAtomicAnd32, U32, Opaque, Opaque, U32, )
OPCODE(BufferAtomicOr32, U32, Opaque, Opaque, U32, )
OPCODE(BufferAtomicXor32, U32, Opaque, Opaque, U32, )
OPCODE(BufferAtomicExchange32, U32, Opaque, Opaque, U32, )
OPCODE(BufferAtomicSwap32, U32, Opaque, Opaque, U32, )

// Vector utility
OPCODE(CompositeConstructU32x2, U32x2, U32, U32, )
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3 changes: 2 additions & 1 deletion src/shader_recompiler/ir/passes/resource_tracking_pass.cpp
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Expand Up @@ -32,7 +32,7 @@ bool IsBufferAtomic(const IR::Inst& inst) {
case IR::Opcode::BufferAtomicAnd32:
case IR::Opcode::BufferAtomicOr32:
case IR::Opcode::BufferAtomicXor32:
case IR::Opcode::BufferAtomicExchange32:
case IR::Opcode::BufferAtomicSwap32:
return true;
default:
return false;
Expand Down Expand Up @@ -136,6 +136,7 @@ IR::Type BufferDataType(const IR::Inst& inst, AmdGpu::NumberFormat num_format) {
case IR::Opcode::ReadConstBufferU32:
case IR::Opcode::StoreBufferU32:
case IR::Opcode::BufferAtomicIAdd32:
case IR::Opcode::BufferAtomicSwap32:
return IR::Type::U32;
default:
UNREACHABLE();
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