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add option to skip n SPI data bits
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danielkucera committed Jan 21, 2023
1 parent 73cb546 commit bcbcfc5
Showing 1 changed file with 8 additions and 0 deletions.
8 changes: 8 additions & 0 deletions decoders/spi/pd.py
Original file line number Diff line number Diff line change
Expand Up @@ -100,6 +100,8 @@ class Decoder(srd.Decoder):
'values': (0, 1)},
{'id': 'bitorder', 'desc': 'Bit order',
'default': 'msb-first', 'values': ('msb-first', 'lsb-first')},
{'id': 'skipbits', 'desc': 'Skip bits from start',
'default': 0},
{'id': 'wordsize', 'desc': 'Word size', 'default': 8},
)
annotations = (
Expand Down Expand Up @@ -131,6 +133,7 @@ def __init__(self):
def reset(self):
self.samplerate = None
self.bitcount = 0
self.bitsskipped = 0
self.misodata = self.mosidata = 0
self.misobits = []
self.mosibits = []
Expand Down Expand Up @@ -200,6 +203,7 @@ def reset_decoder_state(self):
self.misobits = [] if self.have_miso else None
self.mosibits = [] if self.have_mosi else None
self.bitcount = 0
self.bitsskipped = 0

def cs_asserted(self, cs):
active_low = (self.options['cs_polarity'] == 'active-low')
Expand Down Expand Up @@ -310,6 +314,10 @@ def find_clk_edge(self, miso, mosi, clk, cs, first):
elif mode == 3 and clk == 0: # Sample on rising clock edge
return

if self.bitsskipped < self.options["skipbits"]:
self.bitsskipped += 1
return

# Found the correct clock edge, now get the SPI bit(s).
self.handle_bit(miso, mosi, clk, cs)

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