uart: fixed broken testcases

decoders/uart/pd.py

@@ -309,7 +309,7 @@ def put_packet(self, rxtx):
         self.putx_packet(rxtx, [Ann.RX_PACKET + rxtx, [s]])
         self.packet_cache[rxtx] = []
 
-    def handle_packet(self, rxtx, frame_end_sample):
+    def handle_packet(self, rxtx):
         d = 'rx' if (rxtx == RX) else 'tx'
         delim = self.options[d + '_packet_delim']
         plen = self.options[d + '_packet_len']
@@ -319,9 +319,9 @@ def handle_packet(self, rxtx, frame_end_sample):
         # Cache data values until we see the delimiter and/or the specified
         # packet length has been reached (whichever happens first).
         if len(self.packet_cache[rxtx]) == 0:
-            self.ss_packet[rxtx] = self.frame_start[rxtx]
+            self.ss_packet[rxtx] = self.startsample[rxtx] - floor(self.bit_width / 2.0)
         self.packet_cache[rxtx].append(self.datavalue[rxtx])
-        self.es_packet[rxtx] = frame_end_sample
+        self.es_packet[rxtx] = self.samplenum + ceil(self.bit_width / 2.0)
         if self.datavalue[rxtx] == delim or len(self.packet_cache[rxtx]) == plen:
             self.put_packet(rxtx)
 
@@ -359,6 +359,8 @@ def get_data_bits(self, rxtx, signal):
         self.putbin(rxtx, [Bin.RX + rxtx, bdata])
         self.putbin(rxtx, [Bin.RXTX, bdata])
 
+        self.handle_packet(rxtx)
+
         self.databits[rxtx] = []
 
         self.advance_state(rxtx, signal)
@@ -488,7 +490,6 @@ def advance_state(self, rxtx, signal = None, fatal = False, idle = None):
             ss = self.frame_start[rxtx]
             es = self.samplenum + ceil(self.bit_width / 2.0)
             self.handle_frame(rxtx, ss, es)
-            self.handle_packet(rxtx, es)
             self.state[rxtx] = 'WAIT FOR START BIT'
             self.idle_start[rxtx] = frame_end
             return