Merge pull request #52 from slaclab/pre-release

Release Candidate v5.9.0
slaclab · Jul 10, 2023 · 826f76e · 826f76e
2 parents aa552a7 + 99ac0c1
commit 826f76e
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Showing 4 changed files with 33 additions and 18 deletions.
diff --git a/.github/workflows/lcls2_pgp_ci.yml b/.github/workflows/lcls2_pgp_ci.yml
@@ -18,19 +18,19 @@ on: [push]
 
 jobs:
 
-  test:
-    name: Test
-    runs-on: ubuntu-20.04
+  test_and_document:
+    name: Test And Generate Documentation
+    runs-on: ubuntu-22.04
     steps:
 
       # This step checks out a copy of your repository.
-      - uses: actions/checkout@v2
+      - uses: actions/checkout@v3
         with:
           fetch-depth: 0
 
-      - uses: actions/setup-python@v2
+      - uses: actions/setup-python@v4
         with:
-          python-version: 3.8
+          python-version: 3.11
 
       - name: Install dependencies
         run: |
@@ -45,7 +45,7 @@ jobs:
   gen_release:
     name: Generate Release
     runs-on: ubuntu-20.04
-    needs: [test]
+    needs: [test_and_document]
     if: startsWith(github.ref, 'refs/tags/')
     steps:
 
@@ -78,7 +78,7 @@ jobs:
 
   conda_build:
     name: Anaconda Build
-    needs: [test]
+    needs: [test_and_document]
     if: startsWith(github.ref, 'refs/tags/')
     strategy:
       matrix:
@@ -106,6 +106,9 @@ jobs:
           export PATH="${HOME}/miniconda/bin:$PATH"
           source ${HOME}/miniconda/etc/profile.d/conda.sh
           conda config --set always_yes yes
+          conda config --set channel_priority strict
+          conda install -n base conda-libmamba-solver
+          conda config --set solver libmamba
           conda install conda-build anaconda-client conda-verify
           conda update -q conda conda-build
           conda update --all
@@ -124,5 +127,4 @@ jobs:
           export PATH="${HOME}/miniconda/bin:$PATH"
           source ${HOME}/miniconda/etc/profile.d/conda.sh
           conda build --debug conda-recipe --output-folder bld-dir -c tidair-tag -c tidair-packages -c conda-forge
-          anaconda -t ${{ steps.get_image_info.outputs.token }} upload bld-dir/${{ steps.get_image_info.outputs.os }}/*.tar.bz2
-
+          anaconda -t ${{ steps.get_image_info.outputs.token }} upload --force bld-dir/noarch/*.tar.bz2
diff --git a/conda-recipe/meta.yaml b/conda-recipe/meta.yaml
@@ -7,17 +7,18 @@ source:
 
 build:
    number: {{ GIT_DESCRIBE_NUMBER|int }}
+   noarch: python
 
 requirements:
    build:
-     - python<3.8
+     - python>=3.7
      - rogue
      - git
      - gitpython
      - numpy
 
    run:
-     - python
+     - python>=3.7
      - rogue
      - numpy
 

diff --git a/shared/rtl/UltraScale+/TimingRx.vhd b/shared/rtl/UltraScale+/TimingRx.vhd
@@ -47,9 +47,12 @@ entity TimingRx is
       EN_LCLS_II_TIMING_G : boolean := true);
    port (
       -- Reference Clock and Reset
-      userClk156  : in  sl := '0';      -- USE_GT_REFCLK_G = FALSE
-      userClk25   : in  sl := '0';      -- USE_GT_REFCLK_G = FALSE
-      userRst25   : in  sl := '1';      -- USE_GT_REFCLK_G = FALSE
+      userClk156     : in  sl := '0';      -- USE_GT_REFCLK_G = FALSE
+      userClk25      : in  sl := '0';      -- USE_GT_REFCLK_G = FALSE
+      userRst25      : in  sl := '1';      -- USE_GT_REFCLK_G = FALSE
+      timingRxClkOut : out sl;
+      timingRxRstOut : out sl;
+
       -- Trigger Interface
       triggerClk  : in  sl;
       triggerRst  : in  sl;
@@ -189,6 +192,9 @@ architecture mapping of TimingRx is
 
 begin
 
+   timingRxClkOut <= timingRxClk;
+   timingRxRstOut <= timingRxRst;
+
    timingTxRst    <= txUserRst;
    timingRxRstTmp <= rxUserRst or not rxStatus.resetDone;
 

diff --git a/shared/rtl/UltraScale/TimingRx.vhd b/shared/rtl/UltraScale/TimingRx.vhd
@@ -47,9 +47,12 @@ entity TimingRx is
       EN_LCLS_II_TIMING_G : boolean := true);
    port (
       -- Reference Clock and Reset
-      userClk156  : in  sl := '0';      -- USE_GT_REFCLK_G = FALSE
-      userClk25   : in  sl := '0';      -- USE_GT_REFCLK_G = FALSE
-      userRst25   : in  sl := '1';      -- USE_GT_REFCLK_G = FALSE
+      userClk156     : in  sl := '0';      -- USE_GT_REFCLK_G = FALSE
+      userClk25      : in  sl := '0';      -- USE_GT_REFCLK_G = FALSE
+      userRst25      : in  sl := '1';      -- USE_GT_REFCLK_G = FALSE
+      timingRxClkOut : out sl;
+      timingRxRstOut : out sl;
+
       -- Trigger Interface
       triggerClk  : in  sl;
       triggerRst  : in  sl;
@@ -189,6 +192,9 @@ architecture mapping of TimingRx is
 
 begin
 
+   timingRxClkOut <= timingRxClk;
+   timingRxRstOut <= timingRxRst;
+
    timingTxRst    <= txUserRst;
    timingRxRstTmp <= rxUserRst or not rxStatus.resetDone;