Skip to content

Releases: slaclab/surf

Patch Release

10 May 17:04
@ruck314 ruck314
v1.8.3
0fbaf30
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release

Pull Requests

  1. #220 - v1.8.3 release candidate
  2. #222 - PGPv3 6.25Gbps Ultrascale support and SFP I2C revamp
  3. #224 - Migrating optical trasceivers to SFF-8472
  4. #223 - JESD Updates
  5. #219 - adding rxPowerDown and txPowerDown to JESD

Pull Request Details

v1.8.3 release candidate
Author: Larry Ruckman [email protected]
Date: Thu May 10 10:01:37 2018 -0700
Pull: #220 (4143 additions, 2007 deletions, 52 files changed)
Branch: slaclab/pre-release

Notes:

Description

  1. adding rxPowerDown and txPowerDown for JESD
  2. PGPv3 6.25Gbps Ultrascale support and SFP I2C revamp
  3. Adding more pipelining to JESD to help meet timing for high speed (12.5Gbps) applications

JIRA

ESCRYODET-117

PGPv3 6.25Gbps Ultrascale support and SFP I2C revamp
Author: Larry Ruckman [email protected]
Date: Wed May 9 11:21:21 2018 -0700
Pull: #222 (2890 additions, 1355 deletions, 36 files changed)
Branch: slaclab/pgp3-dev

Notes:

Description

  1. Adding support for 6.25Gbps for the Ultrascale FPGA fabric (required for ATLAS)
  2. Depreciating SFP/QSFP/CXP module
  3. Replacing this module with a common SFF-8472 module
  4. Adding Ltc4151 python

Details

This update will break existing .XDC timing constraints. The hierarchy path to RXCLKOUT and TXCLKOUT will need to be updated.

Testing

This build has been tested for 6.25Gbps and regression tested for 10.3125Gbps on KCU1500

Migrating optical trasceivers to SFF-8472
Author: Larry Ruckman [email protected]
Date: Mon May 7 17:44:31 2018 -0700
Pull: #224 (840 additions, 1120 deletions, 18 files changed)
Branch: slaclab/SFF-8472

Notes:

Description

  1. Depreciating SFP/QSFP/CXP module
  2. Replacing this module with a common SFF-8472 module
  3. Adding Ltc4151 python

Note

There is still a lot of work that could be done to make all the SFF-8472 variables into human readable variables. We can add this to the module at a later time.

JESD Updates
Author: Larry Ruckman [email protected]
Date: Wed May 9 13:50:50 2018 -0700
Pull: #223 (1039 additions, 495 deletions, 16 files changed)
Branch: slaclab/jesd-dev

Notes:

Description

Adding more pipeline for performance improvements

adding rxPowerDown and txPowerDown to JESD
Author: Larry Ruckman [email protected]
Date: Wed May 2 18:24:13 2018 -0700
Pull: #219 (264 additions, 207 deletions, 8 files changed)
Branch: slaclab/jesd-pwrdn-support

Notes:

Description

adding rxPowerDown and txPowerDown to JESD

Assets 2
Loading

Patch Release

02 May 16:52
@ruck314 ruck314
v1.8.2
b63060d
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release

Pull Requests

  1. #218 - v1.8.2 release candidate
  2. #217 - minor gtx7 updates
  3. #216 - _Sa56004x.py bit offsets and sizes fix

Pull Request Details

v1.8.2 release candidate
Author: Larry Ruckman [email protected]
Date: Wed May 2 09:49:48 2018 -0700
Pull: #218 (404 additions, 110 deletions, 4 files changed)
Branch: slaclab/pre-release

Notes:

Description

  1. Updates to _Sa56004x.py
  2. Updates to the PGPv3 GTX7

minor gtx7 updates
Author: Larry Ruckman [email protected]
Date: Wed May 2 09:47:41 2018 -0700
Pull: #217 (397 additions, 103 deletions, 3 files changed)
Branch: slaclab/gtx7-dev

Notes:

Description

  1. adding Gtxe2ChannelDummy.vhd
  2. bug fix for Pgp3Gtx7Wrapper.vhd when REFCLK_G=true

_Sa56004x.py bit offsets and sizes fix
Author: Larry Ruckman [email protected]
Date: Thu Apr 26 14:55:17 2018 -0700
Pull: #216 (7 additions, 7 deletions, 1 files changed)
Branch: slaclab/lzts-dev

Notes:

Description

Fixed Sa56004x bit size and offsets according to the specification.

Assets 2
Loading

Patch Release

25 Apr 15:47
@ruck314 ruck314
v1.8.1
58f916e
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release

Pull Requests

  1. #215 - v1.8.1 release candidate
  2. #213 - Updates to PGPv3
  3. #214 - CPSW requires all WO variables to be 32-bit size and 32-bit aligned
  4. #212 - Overhauling Debouncer from shift reg to counter based

Pull Request Details

v1.8.1 release candidate
Author: Larry Ruckman [email protected]
Date: Wed Apr 25 08:43:21 2018 -0700
Pull: #215 (564 additions, 413 deletions, 34 files changed)
Branch: slaclab/pre-release

Notes:

Description

  1. Debouncer Update (#212)
  2. PGPv3 updates (#213)
  3. CPSW YAML updates (#214)

Updates to PGPv3
Author: Larry Ruckman [email protected]
Date: Wed Apr 25 08:33:41 2018 -0700
Pull: #213 (447 additions, 357 deletions, 23 files changed)
Branch: slaclab/pgpv3-gtx7-dev

Notes:

Description

  1. Updating PGPv3 default AXI-lite slave buses
  2. Adding EN_DRP_G to 7series QPLL wrapper
  3. For PGPv3.GTX7, routing txPreCursor, txPostCursor and txDiffCtrl to top level wrapper
  4. Bug fixes for _Pgp3AxiL.py
  5. Bug fix for loopback not being routed to the PHY layer
  6. Updating the PROM's python elapsed time print outs
  7. For PGPv3.GTX7, txDataRdy bug fix
    -- refer to Figure 3-12 in UG476 (v1.12)
  8. bug fixes for protTxStart and protTxSequence
    -- I have verified the fix in GTX7 and verified GTH Ultrascale still work after these changes

JIRA

ATLASDAQ-2

CPSW requires all WO variables to be 32-bit size and 32-bit aligned
Author: Larry Ruckman [email protected]
Date: Wed Apr 25 08:33:24 2018 -0700
Pull: #214 (79 additions, 33 deletions, 10 files changed)
Branch: slaclab/cpsw-yaml

Notes:

Description

CPSW requires all WO variables to be 32-bit size and 32-bit aligned

Overhauling Debouncer from shift reg to counter based
Author: Larry Ruckman [email protected]
Date: Fri Apr 20 13:43:48 2018 -0700
Pull: #212 (38 additions, 23 deletions, 1 files changed)
Branch: slaclab/lzts-dev

Notes:

Description

Debouncer was changed to use a counter instead of a shift register. This implementation will allow to make a longer filter without using excessive resources. The generics had to be changed therefore existing projects using debouncer will have to be modified. Removed old generics : FILTER_SIZE_G, FILTER_INIT_G. New generics : CLK_PERIOD_G, DEBOUNCE_PERIOD_G.

Assets 2
Loading

Minor Release

19 Apr 16:04
@ruck314 ruck314
v1.8.0
8bee8d1
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Minor Release

Pull Requests

  1. #211 - v1.8.0 release candidate
  2. #205 - Some Ethernet Development
  3. #208 - Adding Micron MT28EW BPI PROM support
  4. #209 - SsiPrbsRateGen Update
  5. #207 - In the Ads42lb69Core fixed cross clock domain synchronization
  6. #206 - Reorganizing the AXI source code
  7. #210 - Variable Overlap bug fix in PGPv3

Pull Request Details

v1.8.0 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Apr 19 08:39:28 2018 -0700
Pull: #211 (4842 additions, 1351 deletions, 168 files changed)
Branch: slaclab/pre-release

Notes:

Description

  1. Reorganizing the AXI source code (#206)
  2. In the Ads42lb69Core fixed cross clock domain synchronization (#207)
  3. Adding Micron MT28EW BPI PROM support (#208)
  4. SsiPrbsRateGen Update (#209)
  5. Variable Overlap bug fix in PGPv3 (#210)

Some Ethernet Development
Author: Larry Ruckman [email protected]
Date: Mon Apr 9 10:44:27 2018 -0700
Pull: #205 (3831 additions, 1237 deletions, 69 files changed)
Branch: slaclab/eth-dev

Notes:

Description

  1. bug fix for gtp7/1GbE's Multi-driven net error when lane>1
  2. Adding surf/ethernet/GigEthCore/gtyUltraScale+ source code
  3. Adding surf/ethernet/XauiCore/gtyUltraScale+ source code
  4. Adding Autneg support to surf/ethernet/GigEthCore
  5. Adding GtyUltraScaleQuadPll wrapper
  6. adding ethernet/TenGigEthCore/gtyUltraScale+
  7. adding ethernet/TenGigEthCore/gthUltraScale+

JIRA

ESCORE-341
ESCORE-310
ESCORE-311
ESCORE-340
ESCORE-309
ESCORE-295

Adding Micron MT28EW BPI PROM support
Author: Larry Ruckman [email protected]
Date: Thu Apr 19 08:31:35 2018 -0700
Pull: #208 (821 additions, 2 deletions, 7 files changed)
Branch: slaclab/ESCORE-334
Jira: https://jira.slac.stanford.edu/issues/ESCORE-334

Notes:

Description

Added Micron MT28EW BPI PROM support

JIRA

ESCORE-334

SsiPrbsRateGen Update
Author: Larry Ruckman [email protected]
Date: Thu Apr 19 08:32:15 2018 -0700
Pull: #209 (72 additions, 74 deletions, 2 files changed)
Branch: slaclab/SsiPrbsRateGen

Notes:

Description

  1. Updating VHDL because breaking apart >32-bit SLV into multiple axiSlaveRegister() no longer required
  2. Updating SsiPrbsRateGen.py to rogue v2.8

In the Ads42lb69Core fixed cross clock domain synchronization
Author: Larry Ruckman [email protected]
Date: Tue Apr 10 13:17:50 2018 -0700
Pull: #207 (50 additions, 26 deletions, 2 files changed)
Branch: slaclab/lzts-dev

Notes:

Description

The configuration and ADC data of the Ads42lb69Core are asynchronous. The invert and convert bits of the configuration were used in the ADC data clock domain without synchronization. This could potentially lead to random issues due to metastability. this is the best candidate to cause the issue described in ESLZTS-30.

Reorganizing the AXI source code
Author: Larry Ruckman [email protected]
Date: Thu Apr 19 08:31:12 2018 -0700
Pull: #206 (56 additions, 4 deletions, 84 files changed)
Branch: slaclab/axi-dir-reorg

Notes:

Description

  1. moved packetizer source code from axi/rtl to protocols/packetizer
  2. moved dma source code from axi/rtl to axi/dma
  3. moved bridge source code from axi/rtl to axi/bridge
  4. moved AXI-Lite source code from axi/rtl to axi/axi-lite
  5. moved AXI-stream source code from axi/rtl to axi/axi-stream
  6. moved AXI4/AXI3 source code from axi/rtl to axi/axi-mem

Variable Overlap bug fix in PGPv3
Author: Larry Ruckman [email protected]
Date: Tue Apr 17 19:37:03 2018 -0700
Pull: #210 (12 additions, 8 deletions, 4 files changed)
Branch: slaclab/Pgp3AxiL.py

Notes:

Description

Fixed overlapping bug in python/surf/protocols/pgp/_Pgp3AxiL.py

Assets 2
Loading

Patch Release

04 Apr 05:38
@ruck314 ruck314
v1.7.4
058604c
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Patch Release

Pull Requests

  1. #203 - Updates to Clink python to support latest rogue
  2. #201 - Ltc2270 Python Register Mapping Bug Fix
  3. #202 - Python bug fix for AxiMicronP30.py

Pull Request Details

Updates to Clink python to support latest rogue
Author: Ryan Herbst [email protected]
Date: Tue Apr 3 22:14:00 2018 -0700
Pull: #203 (16 additions, 16 deletions, 2 files changed)
Branch: slaclab/clink_deprecate

Notes:

Remove deprecated class method decorators for serial send commands.

Fix reqFrame call for new API in serial send commands.

Ltc2270 Python Register Mapping Bug Fix
Author: Larry Ruckman [email protected]
Date: Tue Apr 3 22:14:49 2018 -0700
Pull: #201 (11 additions, 11 deletions, 1 files changed)
Branch: slaclab/Ltc2270-python-fix

Notes:

Description

Fixed the register mapping. I didn't know about this until rogue v2.7.0, which outputs all overlapping registers.

Python bug fix for AxiMicronP30.py
Author: Larry Ruckman [email protected]
Date: Tue Apr 3 22:15:11 2018 -0700
Pull: #202 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/AxiMicronP30

Notes:

Description

Not enough "size" allocated for _rawWrite/_rawRead. Fixed it in d61db37 commit.

Assets 2
Loading

Release v1.7.3

02 Apr 18:56
@bengineerd bengineerd
v1.7.3
5f80d9f
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
Release v1.7.3

Overview

This is a patch release with a few critical bug fixes and some small enhancements as described in the Pull Request list below.

Pull Requests

  1. #196 - Added several new pyrogue Devices and enhanced some existing ones
  2. #199 - Fixed RSSI TX FSM bug
  3. #195 - Updates to UDP pyrogue Devices
  4. #192 - Better display of IP address and port numbers
  5. #197 - RSSI FlowControl Bug Fix

Pull Request Details

Added several new pyrogue Devices and enhanced some existing ones
Author: Larry Ruckman [email protected]
Date: Tue Mar 27 14:56:39 2018 -0700
Pull: #196 (1323 additions, 336 deletions, 14 files changed)
Branch: slaclab/overlap_var-llr

Notes:

Description

  1. Updates for rogue v2.7.0
  2. Added SA56004ATK, LTC2945, and TCN75AVOA713 device classes
  3. Updated _AxiSysMonUltraScale.py to outputs simliar to XADC
  4. Updated the RSSI bandwidth/rate variable names

JIRA

ESCORE-330
ESCRYODET-94

Fixed RSSI TX FSM bug
Author: Larry Ruckman [email protected]
Date: Mon Apr 2 10:15:57 2018 -0700
Pull: #199 (209 additions, 109 deletions, 5 files changed)
Branch: slaclab/rssi-dev

Notes:

Description

  1. RSSI TX FSM flow control bug fix (1fcfb71)
  2. V1 Packeterizer code clean up (08a98be/5111f10)
  3. Added auto polling to _SsiPrbsRx.py and _SsiPrbsTx.py (d398dd5)

I have regression tested this on the dev-board-example target for this corner case for both _rawWrite() and PRBS TX/RX streams.

JIRA

ESCORE-339

Updates to UDP pyrogue Devices
Author: Larry Ruckman [email protected]
Date: Wed Mar 21 17:19:10 2018 -0700
Pull: #195 (42 additions, 37 deletions, 3 files changed)
Branch: slaclab/udp-link-var

Notes:

  1. Updating any python with size if rawWrite/rawRead used
  2. Updating the UDP LinkVariables

Better display of IP address and port numbers
Author: Larry Ruckman [email protected]
Date: Fri Mar 16 15:27:44 2018 -0700
Pull: #192 (55 additions, 0 deletions, 2 files changed)
Branch: slaclab/ESCORE-332
Jira: https://jira.slac.stanford.edu/issues/ESCORE-332

Notes:

Added LinkVariable to make the UDP IP address and Port number human readable

RSSI FlowControl Bug Fix
Author: Larry Ruckman [email protected]
Date: Wed Mar 28 13:54:12 2018 -0700
Pull: #197 (2 additions, 1 deletions, 1 files changed)
Branch: slaclab/rssi-dev

Notes:

Description

We previously had this:

constant FIFO_PAUSE_THRESH_C : positive := ((2**FIFO_ADDR_WIDTH_C)-1) - 16;  -- FIFO_FULL - padding (128 bytes)

SEGMENT_ADDR_SIZE_G = 7, which is 2^7 = 128 words
128 words (1024B) > 16 padding
In this pull request, we change the threshold to this:

constant FIFO_PAUSE_THRESH_C : positive := (2**FIFO_ADDR_WIDTH_C) - (2**(SEGMENT_ADDR_SIZE_G+1));  -- pause threshold = FIFO_FULL - (2 x segment buffers)

This makes sure there's 2 times more buffer room in the FIFO before bursting from the BRAM to the FIFO when SEGMENT_ADDR_SIZE_G > 6, FIFO_PAUSE_THRESH_C becomes effectively (2**FIFO_ADDR_WIDTH_C)/2.
I have confirmed in dev-board-example that this works.
slaclab/dev-board-examples@e61df85

JIRA

ESROGUE-202 (related)

Assets 2
Loading

SURF v1.7.2

15 Mar 19:03
@bengineerd bengineerd
v1.7.2
f8e0ba9
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
SURF v1.7.2

Pull Requests

  1. #191 - Remove bit_vector use in Crc32Rtl

Pull Request Details

Remove bit_vector use in Crc32Rtl
Author: Benjamin Reese [email protected]
Date: Thu Mar 15 11:58:50 2018 -0700
Pull: #191 (19 additions, 17 deletions, 1 files changed)
Branch: slaclab/ben-crc-fix

Notes:

The CRC_INIT generic was a bit_vector. There was an improper conversion call that caused synthesis to fail. As part of this fix, all bit_vector use as been removed.

Assets 2
Loading

SURF v1.7.1

14 Mar 23:05
@bengineerd bengineerd
v1.7.1
5d07075
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
SURF v1.7.1

Pull Requests

  1. #190 - Add back GthUltrascaleQuadPll EN_DRP_G generic

Pull Request Details

Add back GthUltrascaleQuadPll EN_DRP_G generic
Author: Benjamin Reese [email protected]
Date: Wed Mar 14 16:01:17 2018 -0700
Pull: #190 (3 additions, 2 deletions, 1 files changed)
Branch: slaclab/en-drp

Notes:

This generic somehow got erroneously removed in #147.

Assets 2
Loading

SURF v1.7.0

14 Mar 19:59
@bengineerd bengineerd
v1.7.0
5fe843f
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.
Compare
Choose a tag to compare
SURF v1.7.0

Pull Requests

  1. #178 - ESROGUE-153 - AxiStreamPacketizerV2 enhancements
  2. #147 - Remove AXI_ERROR_RESP_G
  3. #188 - Pyrogue Device fixes for Ad5780 and Ltc2270
  4. #186 - ESLCOMMON-205 - Set proper header on Pgp3 opcode transmission

Pull Request Details

ESROGUE-153 - AxiStreamPacketizerV2 enhancements
Author: Benjamin Reese [email protected]
Date: Tue Mar 13 17:04:04 2018 -0700
Pull: #178 (834 additions, 471 deletions, 12 files changed)
Branch: slaclab/ESROGUE-153
Jira: https://jira.slac.stanford.edu/issues/ESROGUE-153

Notes:

Lots of changes to AxiStreamPacketizerV2 and modules that use it

AxiStreamPacketizerV2/AxiStreamDepacketizerV2

  • Fixed some TKEEP bugs in the Packetizer
  • Packetizer/Depacketizer now have generics to optionally include the header and tail in the CRC calculation.
  • The Packetizer protocol has changed so that the CRC is cumulative over every packet of a frame.

RSSI

  • Enable CRC by default when interleaving

PGP3

  • The change to cumulative CRC is carried into the PGP3 protocol
  • This means that PGP3 instances built previously will not be compatible with this!

Remove AXI_ERROR_RESP_G
Author: Benjamin Reese [email protected]
Date: Wed Mar 14 09:28:50 2018 -0700
Pull: #147 (368 additions, 801 deletions, 152 files changed)
Branch: slaclab/rem-axi-err-resp

Notes:

I've gone through every module in SURF and removed the AXI_ERROR_RESP_G generic.

AxiLiteCrossbar and AxiLiteAsync still have it. If you need to mask AXI errors, you should do it at the top-most crossbar or synchronizer, where you connect to the bus that cannot tolerate errors.

AxiLiteEmpty also still has it, as you may want a particular instance to respond with OK to every access.

I also left it in AxiStreamDmaV2, because the generic is passed down to a crossbar which may be the top level. If this is not the case then we should remove it here too

This will obviously break some builds, but the fix is pretty easy. Just remove the generic association from the instantiation.

Pyrogue Device fixes for Ad5780 and Ltc2270
Author: Larry Ruckman [email protected]
Date: Wed Mar 14 09:57:55 2018 -0700
Pull: #188 (8 additions, 4 deletions, 2 files changed)
Branch: slaclab/lcls2-prl-dev

Notes:

Ad5780 - Fixed Variable/method name conflict
Ltc2779 - Properly name array Variables

ESLCOMMON-205 - Set proper header on Pgp3 opcode transmission
Author: Benjamin Reese [email protected]
Date: Mon Mar 12 12:18:51 2018 -0700
Pull: #186 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/ESLCOMMON-205
Jira: https://jira.slac.stanford.edu/issues/ESLCOMMON-205

Notes:

The header field wasn't being set to PGP3_K_HEADER_C ("10") when sending OpCodes. This has been fixed.

https://jira.slac.stanford.edu/browse/ESLCOMMON-205

Assets 2
Loading

v1.3.0

02 Jun 19:27
@slacrherbst slacrherbst
v1.3.0
cce605b
Compare
Choose a tag to compare
v1.3.0

Stable version after reorganization.

Assets 2
Loading