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Patch Release v2.0.7

11 Feb 22:51
@bengineerd bengineerd
v2.0.7
2020d6f
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Patch Release v2.0.7

Pull Requests

  1. #608 - removing #!/usr/bin/env python & misc code header clean up
  2. #611 - Add anaconda release of Surf
  3. #609 - Modify ClinkSerial to show string in sendString and response
  4. #610 - mapping JESD CmdClearErrors() to countReset()

Pull Request Details

Release Candidate - Patch Release v2.0.7

removing #!/usr/bin/env python & misc code header clean up
Author: Larry Ruckman [email protected]
Date: Fri Feb 7 12:35:57 2020 -0800
Pull: #608 (11 additions, 263 deletions, 130 files changed)
Branch: slaclab/py-patch

Notes:

Description

  • removing #!/usr/bin/env python for all non-executable python scripts
  • misc code header clean up

Add anaconda release of Surf
Author: Ryan Herbst [email protected]
Date: Tue Feb 11 11:52:06 2020 -0800
Pull: #611 (161 additions, 0 deletions, 6 files changed)
Branch: slaclab/conda_release

Notes:

This PR add an anaconda release of the surf library

Modify ClinkSerial to show string in sendString and response
Author: Larry Ruckman [email protected]
Date: Fri Feb 7 15:50:01 2020 -0800
Pull: #609 (14 additions, 5 deletions, 3 files changed)
Branch: bhill-slac/serial-diags

Notes:

Camera testing and support is easier if we can see the string being sent and the response.

Description

Adds a print statement in ClinkSerialTx::sendString() to show the msg being sent.
Also adds support for printing the response after the ACK so we can see response
to queries such as serialNumber, camera model ID, etc.

Example output:
sendString: @id?
Got ACK Response
recvString: @"OPAL-1000m/CL S/N:135043

mapping JESD CmdClearErrors() to countReset()
Author: Benjamin Reese [email protected]
Date: Tue Feb 11 14:19:38 2020 -0800
Pull: #610 (7 additions, 0 deletions, 2 files changed)
Branch: slaclab/jesd-cnt-rst

Notes:

Description

  • Adds support to clear all the JESD status error counters using the GUI "CountReset" button
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Patch Release

06 Feb 23:08
@ruck314 ruck314
v2.0.6
45e4f00
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Patch Release

Pull Requests

  1. #607 - v2.0.6 release candidate
  2. #603 - Ethernet RAM optimizations
  3. #604 - Adding no clock feedback mode to the Ads42lb69 core
  4. #605 - AxiAds42lb69DeserBit.vhd: bug fix when XIL_DEVICE_G=7SERIES
  5. #606 - SynchronizerOneShotCntVector: Bug fix for freq(wrClk) > freq(rdClk)

Pull Request Details

v2.0.6 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Feb 6 15:05:47 2020 -0800
Pull: #607 (453 additions, 204 deletions, 26 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Adding no clock feedback mode to the Ads42lb69 core #604
  • AxiAds42lb69DeserBit.vhd: bug fix when XIL_DEVICE_G=7SERIES #605
  • SynchronizerOneShotCntVector: Bug fix for freq(wrClk) > freq(rdClk) #606
  • Ethernet RAM optimizations #603

Ethernet RAM optimizations
Author: Larry Ruckman [email protected]
Date: Thu Feb 6 13:46:26 2020 -0800
Pull: #603 (337 additions, 161 deletions, 21 files changed)
Branch: slaclab/eth-dev

Notes:

Description

  • TDEST not used internally of EthMacTop.vhd
    • Doing this logic optimization to fit into two 72-bit width RAMs but also maintaining EMAC_AXIS_CONFIG_C with external application to prevent possible TDEST issues
  • add support for (MEMORY_TYPE_G=ultra) and (GEN_SYNC_FIFO_G=false) in SsiFifo
  • updating the Ultscale+ ETH module to use URAMs for ETH RX FIFO
    • 2 URAMs per ETH RX channel

Adding no clock feedback mode to the Ads42lb69 core
Author: Larry Ruckman [email protected]
Date: Tue Feb 4 11:48:50 2020 -0800
Pull: #604 (49 additions, 39 deletions, 4 files changed)
Branch: slaclab/wave8_dev

Notes:

Added no clock feedback mode. Fixed some DRC errors related to IDELAYCTRL in 7 series.

AxiAds42lb69DeserBit.vhd: bug fix when XIL_DEVICE_G=7SERIES
Author: Larry Ruckman [email protected]
Date: Tue Feb 4 12:51:38 2020 -0800
Pull: #605 (62 additions, 3 deletions, 1 files changed)
Branch: slaclab/AxiAds42lb69DeserBit

Notes:

Description

  • resolves issue where a 7-series build does NOT find the Ultrascale source code

SynchronizerOneShotCntVector: Bug fix for freq(wrClk) > freq(rdClk)
Author: Larry Ruckman [email protected]
Date: Wed Feb 5 11:32:24 2020 -0800
Pull: #606 (5 additions, 1 deletions, 1 files changed)
Branch: slaclab/ESCORE-532
Jira: https://jira.slac.stanford.edu/issues/ESCORE-532

Notes:

Description

  • SynchronizerOneShotCntVector would previusly freeze if freq(wrClk) > freq(rdClk)
  • Gating the FIFO write with not(AFULL) to prevent this latching state
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Patch Release

30 Jan 22:33
@ruck314 ruck314
v2.0.5
5cb8fd2
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Patch Release

Pull Requests

  1. #601 - v2.0.5 release candidate
  2. #596 - overhauled SsiFifo.vhd and some misc. ETH updates
  3. #593 - Updates to Inferred/XPM wr/rd count reporting
  4. #600 - optmized SynchronizerOneShotCntVector for logic resources
  5. #594 - adding AXIL_PROXY_G to AxiI2cEeprom.vhd & AxiI2cRegMaster.vhd
  6. #597 - AxiStreamFifoV2: resolved bug in mTLastTUser
  7. #602 - Clink Framer Bug Fix
  8. #598 - exposing Si5345's booting status to top-level
  9. #595 - changed MEMORY_TYPE_G from block to distributed
  10. #592 - Adding SYNTH_MODE_G to Pgp3GthUs.vhd

Pull Request Details

v2.0.5 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Jan 30 14:31:01 2020 -0800
Pull: #601 (2260 additions, 1045 deletions, 35 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Updates to Inferred/XPM wr/rd count reporting #593
  • changed MEMORY_TYPE_G from block to distributed #595
  • Adding SYNTH_MODE_G to Pgp3GthUs.vhd #592
  • AxiStreamFifoV2: resolved bug in mTLastTUser #597
  • exposing Si5345's booting status to top-level #598
  • adding AXIL_PROXY_G to AxiI2cEeprom.vhd & AxiI2cRegMaster.vhd #594
  • overhauled SsiFifo.vhd and some misc. ETH updates #596
  • optmized SynchronizerOneShotCntVector for logic resources #600
  • Clink Framer Bug Fix #602

overhauled SsiFifo.vhd and some misc. ETH updates
Author: Larry Ruckman [email protected]
Date: Wed Jan 29 10:26:13 2020 -0800
Pull: #596 (1398 additions, 876 deletions, 19 files changed)
Branch: slaclab/SsiFifo-patch

Notes:

Description

  • overhauled the buggy SsiFifo.vhd
    • depreciated the SsiFifo.EN_FRAME_FILTER_G
  • placeholder for future TDEST_INTERLEAVE_C in AxiStreamPkg.vhd
  • exposing EthMacRxFifo.vhd's SYNTH_MODE_G&MEMORY_TYPE_G
  • fixed typo in AxiStreamFifoV2.vhd
  • bug fix for EthMacTxPause.vhd
    • remPauseCnt = pauseTime/2 when pause frame sent
  • bug fix for DspComparator.vhd
  • updating the default pauseThresh for JUMBO frame in cache
  • adding EthMacPauseTb.vhd

Updates to Inferred/XPM wr/rd count reporting
Author: Larry Ruckman [email protected]
Date: Thu Jan 23 14:03:18 2020 -0800
Pull: #593 (474 additions, 59 deletions, 4 files changed)
Branch: slaclab/ESCORE-521
Jira: https://jira.slac.stanford.edu/issues/ESCORE-521

Notes:

Description

  • adding FwftCntTb.vhd simulation testbed
  • bug fix for FifoXpm read/write count behavior
    • Also added TPD_G to the FifoXpm outputs
  • bug fix in inferred FIFO wr/rd count reporting

optmized SynchronizerOneShotCntVector for logic resources
Author: Larry Ruckman [email protected]
Date: Thu Jan 30 14:26:18 2020 -0800
Pull: #600 (168 additions, 37 deletions, 2 files changed)
Branch: slaclab/SynchronizerOneShotCntVector

Notes:

Description

  • based on my thought process from PR #599
  • Using a single FIFO instead of 1 FIFO per status counter bus

Resource Usage

Using the Default generics:

      TPD_G           : time     := 1 ns;  -- Simulation FF output delay
      RST_POLARITY_G  : sl       := \'1\';  -- \'1\' for active HIGH reset, \'0\' for active LOW reset
      RST_ASYNC_G     : boolean  := false;  -- true if reset is asynchronous, false if reset is synchronous
      COMMON_CLK_G    : boolean  := false;  -- True if wrClk and rdClk are the same clock
      RELEASE_DELAY_G : positive := 3;  -- Delay between deassertion of async and sync resets
      IN_POLARITY_G   : slv      := "1";  -- 0 for active LOW, 1 for active HIGH (for statusIn port)
      USE_DSP_G       : string   := "no";  -- "no" for no DSP implementation, "yes" to use DSP slices
      SYNTH_CNT_G     : slv      := "1";  -- Set to 1 for synthesizing counter RTL, \'0\' to not synthesis the counter
      CNT_RST_EDGE_G  : boolean  := true;  -- true if counter reset should be edge detected, else level detected
      CNT_WIDTH_G     : positive := 32;   -- Counters\' width
      WIDTH_G         : positive := 16);  -- Status vector width

Old Usage:
SyncStatusVector

New Usage:
SynchronizerOneShotCntVector

adding AXIL_PROXY_G to AxiI2cEeprom.vhd & AxiI2cRegMaster.vhd
Author: Larry Ruckman [email protected]
Date: Wed Jan 29 09:18:55 2020 -0800
Pull: #594 (104 additions, 36 deletions, 3 files changed)
Branch: slaclab/AXIL_PROXY_G

Notes:

Description

  • Adding this AxiLite Proxy shim layer to our common AXI-Lite to I2C wrappers
  • Lots of other changes in the code due to emacs vhdl beautify

JIRA

ESROGUE-424

AxiStreamFifoV2: resolved bug in mTLastTUser
Author: Larry Ruckman [email protected]
Date: Tue Jan 28 10:12:47 2020 -0800
Pull: #597 (62 additions, 26 deletions, 3 files changed)
Branch: slaclab/ESCORE-525
Jira: https://jira.slac.stanford.edu/issues/ESCORE-525

Notes:

Description

  • mTLastTUser can be out of phase of mAxisMaster when (VALID_THOLD_G/=1) and ( (FIFO_CONFIG_C.TDATA_BYTES_C /= MASTER_AXI_CONFIG_G.TDATA_BYTES_C) or (PIPE_STAGES_G/=0) )
    • mapping mTLastTUser through the AxiStreamResize/AxiStreamPipeline sideband to resovle this issue
  • adding AxiStreamPipeline sideband feature
  • adding AxiStreamResize sideband feature

Clink Framer Bug Fix
Author: Larry Ruckman [email protected]
Date: Thu Jan 30 14:26:11 2020 -0800
Pull: #602 (48 additions, 6 deletions, 2 files changed)
Branch: slaclab/clink-patch

Notes:

Description

  • bug fix when tlast set but r.byteData.lv = '0'
  • fixed code comment typos for AxiStreamBytePacker.vhd

JIRA

ESCORE-528

exposing Si5345's booting status to top-level
Author: Larry Ruckman [email protected]
Date: Wed Jan 29 09:08:39 2020 -0800
Pull: #598 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/Si5345-update

Notes:

Description

  • Useful to have during the power-up and init processes when the Si5345's Loss of Lock (LOL) port is not connected to the FPGA

changed MEMORY_TYPE_G from block to distributed
Author: Larry Ruckman [email protected]
Date: Fri Jan 24 11:43:23 2020 -0800
Pull: #595 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/SsiCmdMaster-update

Notes:

Description

  • updating default FIFO_ADDR_WIDTH_G=5
    • compensate for RD/WR latency when GEN_SYNC_FIFO_G=false
  • optimized for LUTRAM (instead of BRAM) since the default FIFO_ADDR_WIDTH_G=5

Adding SYNTH_MODE_G to Pgp3GthUs.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jan 24 11:48:36 2020 -0800
Pull: #592 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/Pgp3GthUs-patch

Notes:

Description

  • Adding SYNTH_MODE_G to Pgp3GthUs.vhd
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Patch Release

21 Jan 19:42
@ruck314 ruck314
v2.0.4
ea9d8a2
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Patch Release

Pull Requests

  1. #585 - v2.0.4 release candidate
  2. #567 - Add SlvDelayFifo Module
  3. #580 - Add meta data location to write dma
  4. #587 - exposing the GigE MMCM's clk/rst
  5. #584 - Fix generic name when used, MAXIS_CONFIG_G -> MASTER_AXI_CONFIG_G
  6. #586 - Move scripts to proper directory
  7. #588 - Exposing SYNTH_MODE_G in FifoMux.vhd

Pull Request Details

v2.0.4 release candidate
Author: Larry Ruckman [email protected]
Date: Tue Jan 21 11:39:41 2020 -0800
Pull: #585 (287 additions, 40 deletions, 19 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Add SlvDelayRam and SlvDelayFifo Modules #567
  • Add meta data location to write dma #580
  • Fix generic name when used, MAXIS_CONFIG_G -> MASTER_AXI_CONFIG_G #584
  • Move scripts to proper directory #586
  • Exposing SYNTH_MODE_G in FifoMux.vhd #588
  • exposing the GigE MMCM's clk/rst #587

Add SlvDelayFifo Module
Author: Benjamin Reese [email protected]
Date: Tue Jan 21 11:30:15 2020 -0800
Pull: #567 (160 additions, 9 deletions, 3 files changed)
Branch: slaclab/timestamp-dev

Notes:

Description

This PR adds a new module:

  • SlvDelayFifo
    • Delay an SLV by a specified number of clock cycles by writing entries into a FIFO and waiting N cycles before popping them out.

There is also some minor code cleanup. In AxiStreamFifoV2, the sAxisCtrl output has been given a default value. In the case where FIFO_FIXED_THRESH_G=false, it was not being assigned a value until the first clock cycle. Giving it a default value allows it to be "paused" until the first clock cycles instead of "unknown".

Add meta data location to write dma
Author: Ryan Herbst [email protected]
Date: Wed Jan 15 15:44:12 2020 -0800
Pull: #580 (71 additions, 13 deletions, 2 files changed)
Branch: slaclab/gpu_meta

Notes:

This PR adds support for writing dma meta data to a particular location after a dma write transaction.

exposing the GigE MMCM's clk/rst
Author: Larry Ruckman [email protected]
Date: Tue Jan 21 11:35:13 2020 -0800
Pull: #587 (42 additions, 6 deletions, 6 files changed)
Branch: slaclab/GigEth-wrap

Notes:

Description

  • Useful to get access to this clk/rst in some applications
    • Instead of dropping down another MMCM (or PLL) to generate the same clk/rst

Fix generic name when used, MAXIS_CONFIG_G -> MASTER_AXI_CONFIG_G
Author: Larry Ruckman [email protected]
Date: Wed Jan 15 17:36:03 2020 -0800
Pull: #584 (6 additions, 6 deletions, 1 files changed)
Branch: slaclab/jmdewart-patch1

Notes:

Description

  • Generic map definition defines MASTER_AXI_CONFIG_G, code in module used MAXIS_CONFIG_G, fix to be consistent.

Move scripts to proper directory
Author: Larry Ruckman [email protected]
Date: Thu Jan 16 16:45:17 2020 -0800
Pull: #586 (5 additions, 5 deletions, 6 files changed)
Branch: slaclab/move_scripts

Notes:

This PR moves scripts from the python/tools directory to the scripts directory. Having tools under python violates our firmware repository convention and could results in namespace conflicts when the contents of python are installed with a release.

I also have moved the other top level test and documentation scripts in the scripts directory.

Exposing SYNTH_MODE_G in FifoMux.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jan 17 14:54:26 2020 -0800
Pull: #588 (3 additions, 1 deletions, 1 files changed)
Branch: slaclab/FifoMux-patch

Notes:

Description

  • Allows the user to build the FifoMux with XPM
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Patch Release

15 Jan 19:26
@ruck314 ruck314
v2.0.3
e3a17a0
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Pull Requests

  1. #583 - v2.0.3 release candidate
  2. #581 - Axi stream monitoring updates
  3. #582 - Updates for epix development (SACI, ssi_printf, AnalogDevices/ad9249)

Pull Request Details

v2.0.3 release candidate
Author: Larry Ruckman [email protected]
Date: Wed Jan 15 11:06:06 2020 -0800
Pull: #583 (497 additions, 218 deletions, 10 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Updates for epix development (SACI, ssi_printf, AnalogDevices/ad9249) #582
  • Axi stream monitoring updates #581

Axi stream monitoring updates
Author: Larry Ruckman [email protected]
Date: Thu Jan 9 15:58:02 2020 -0800
Pull: #581 (479 additions, 212 deletions, 6 files changed)
Branch: slaclab/AxiStreamMonitoring-update

Notes:

Description

  • adding FrameSize support to AxiStreamMon
  • exposing AXIS_CONFIG_G to register space
  • deprecating AxiStreamMonitoring device class
  • reorg of register space with respect to channels
    • Easier to view when using large number of AXIS lanes

Updates for epix development (SACI, ssi_printf, AnalogDevices/ad9249)
Author: Larry Ruckman [email protected]
Date: Fri Jan 10 16:02:06 2020 -0800
Pull: #582 (18 additions, 6 deletions, 4 files changed)
Branch: slaclab/epix-dev

Notes:

Description

  • Fixing saciClk not present (when SACI_CLK_HALF_PERIOD_C=64)
  • help to close timing at higher clock frequency
  • Microblaze cannot make 1 byte writes to the AxiDualPortRam anymore.
    • ixing in the ssi_printf by changingXil_Out8 to Xil_Out32.
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Patch Release

07 Jan 17:31
@ruck314 ruck314
v2.0.2
6f95c28
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Pull Requests

  1. #579 - v2.0.2 release candidate
  2. #578 - Idelaye3Wrapper/Odelaye3Wrapper Usage: syntax bug fix
  3. #577 - Update LICENSE.txt
  4. #576 - Sff8472.py Python Bug Fix
  5. #575 - BoxcarIntegrator.vhd: bug fix for writing to RAM
  6. #574 - removed space in Ltc2945.py variable name

Pull Request Details

v2.0.2 release candidate
Author: Larry Ruckman [email protected]
Date: Tue Jan 7 09:27:49 2020 -0800
Pull: #579 (11 additions, 11 deletions, 8 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • removed space in Ltc2945.py variable name #574
  • BoxcarIntegrator.vhd: bug fix for writing to RAM #575
  • Sff8472.py Python Bug Fix #576
  • Idelaye3Wrapper/Odelaye3Wrapper Usage: syntax bug fix #578
  • Update LICENSE.txt #577

Idelaye3Wrapper/Odelaye3Wrapper Usage: syntax bug fix
Author: Larry Ruckman [email protected]
Date: Tue Jan 7 09:21:02 2020 -0800
Pull: #578 (7 additions, 7 deletions, 4 files changed)
Branch: slaclab/iowrapper-bug-fix

Notes:

Description

  • syntax bug fix for all Idelaye3Wrapper/Odelaye3Wrapper used in SURF FW lib

Update LICENSE.txt
Author: Larry Ruckman [email protected]
Date: Tue Jan 7 09:21:13 2020 -0800
Pull: #577 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/LICENSE-txt-2020

Notes:

Description

  • Updating for year 2020

Sff8472.py Python Bug Fix
Author: Larry Ruckman [email protected]
Date: Thu Dec 19 10:32:55 2019 -0800
Pull: #576 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/Sff8472-python-bug-fix

Notes:

Description

  • removed space in RemoteVariable.name

BoxcarIntegrator.vhd: bug fix for writing to RAM
Author: Larry Ruckman [email protected]
Date: Tue Dec 17 14:39:09 2019 -0800
Pull: #575 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/BoxcarIntegrator-bug-fix

Notes:

Description

  • The RAM write enable strobe was previously 1 cycle out of phase of the write data bus
  • This change uses the registered value of wea, aaddra and dina

removed space in Ltc2945.py variable name
Author: Larry Ruckman [email protected]
Date: Tue Dec 17 09:47:05 2019 -0800
Pull: #574 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/Ltc2945

Notes:

Description

  • Updating to CamelCase variable name
  • Resolves this bug in rogue software:
Rogue/pyrogue version v4.6.0-1-g382ece2c. https://github.com/slaclab/rogue
WARNING:pyrogue.Device.Ltc4151.BoardPwr:Node ADC Input with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ltc4151.BoardPwr:Node ADC Input with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ltc4151.BoardPwr:Node ADC Input with one or more special characters will cause lookup errors.
WARNING:pyrogue.Device.Ltc4151.BoardPwr:Node ADC Input with one or more special characters will cause lookup errors.
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Patch Release

07 Jan 17:31
@ruck314 ruck314
v2.0.1
3c35ca4
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Pull Requests

  1. #573 - v2.0.1 release candidate
  2. #566 - Updating or Removing the last of "work." modules and Ultrscale IODELAY wrapper updates
  3. #572 - Reverting "bypassing work around for back-to-back ETH frames for EthMacRxImportXgmii.vhd"
  4. #568 - protocols/xvc-udp/ruckus.tcl bug fix
  5. #565 - AxiSpiMaster: exposing a copy of the shadow memory
  6. #571 - XauiReg.vhd Bug fix
  7. #570 - bug fix for protocols/xvc-udp/ruckus.tcl
  8. #569 - Ignore the Microblaze autogenerated .TCL files from CopyBdCores()

Pull Request Details

v2.0.1 release candidate
Author: Larry Ruckman [email protected]
Date: Fri Dec 13 10:41:39 2019 -0800
Pull: #573 (152 additions, 873 deletions, 17 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • AxiSpiMaster: exposing a copy of the shadow memory #565
  • Ignore the Microblaze autogenerated .TCL files from CopyBdCores() #569
  • protocols/xvc-udp/ruckus.tcl bug fix #568
  • Updating or Removing the last of "work." modules and Ultrscale IODELAY wrapper updates #566
  • bug fix for protocols/xvc-udp/ruckus.tcl #570
  • XauiReg.vhd Bug fix #571
  • Reverting "bypassing work around for back-to-back ETH frames for EthMacRxImportXgmii.vhd" #572

Updating or Removing the last of "work." modules and Ultrscale IODELAY wrapper updates
Author: Larry Ruckman [email protected]
Date: Thu Dec 5 13:40:42 2019 -0800
Pull: #566 (33 additions, 779 deletions, 12 files changed)
Branch: slaclab/remaining-work-lib

Notes:

Description

  • updating from work.AxiStreamSim to surf.RogueTcpStreamWrap
  • capatizing all the Makefile
  • removing vcs_tb.vhd and its obsolete dependences
  • updating all IDELAYE3 to surf.Idelaye3Wrapper
  • updating all ODELAYE3 to surf.Odelaye3Wrapper
  • depreciating obsolete dma_tb.vhd

Reverting "bypassing work around for back-to-back ETH frames for EthMacRxImportXgmii.vhd"
Author: Larry Ruckman [email protected]
Date: Thu Dec 12 16:14:27 2019 -0800
Pull: #572 (41 additions, 37 deletions, 1 files changed)
Branch: slaclab/ESCORE-514-patch5
Jira: https://jira.slac.stanford.edu/issues/ESCORE-514-patch5

Notes:

Description

  • cab0312#diff-796d952a0151e39fce4245e3019d989e
  • There a weird "feature" in the 10GbE PHY where it will strip away the intergap characters and make the ETH frame back-to-back. This only happens if the two ETH frames are min. ETH spacing (measured from commercial ETH NIC card). This works around detects the back-to-back condition and inserts a gap that required for the downstream logic.
  • However it appears that it is causing more issues than fixes
  • This PR bypasses this "work around" and we can re-investigate this "back-to-back" (no gap) issue at a later time

protocols/xvc-udp/ruckus.tcl bug fix
Author: Larry Ruckman [email protected]
Date: Thu Dec 5 13:36:38 2019 -0800
Pull: #568 (34 additions, 29 deletions, 1 files changed)
Branch: slaclab/xvc-udp-ruckus-bug-fix

Notes:

Description

  • Adding virtex Ultrascale+ HBM type to if statement

AxiSpiMaster: exposing a copy of the shadow memory
Author: Larry Ruckman [email protected]
Date: Tue Dec 3 14:08:08 2019 -0800
Pull: #565 (24 additions, 23 deletions, 1 files changed)
Branch: slaclab/AxiSpiMaster-update

Notes:

Description

  • AxiSpiMaster: exposing a copy of the shadow memory's RAM interface

XauiReg.vhd Bug fix
Author: Larry Ruckman [email protected]
Date: Wed Dec 11 11:19:33 2019 -0800
Pull: #571 (17 additions, 5 deletions, 1 files changed)
Branch: slaclab/ESCORE-515
Jira: https://jira.slac.stanford.edu/issues/ESCORE-515

Notes:

Description

bug fix for protocols/xvc-udp/ruckus.tcl
Author: Larry Ruckman [email protected]
Date: Mon Dec 9 11:09:25 2019 -0800
Pull: #570 (2 additions, 1 deletions, 1 files changed)
Branch: slaclab/zynquplusRFSOC

Notes:

Description

  • Adding the missing zynquplusRFSOC type to if statement

Ignore the Microblaze autogenerated .TCL files from CopyBdCores()
Author: Larry Ruckman [email protected]
Date: Thu Dec 5 13:36:20 2019 -0800
Pull: #569 (2 additions, 0 deletions, 1 files changed)
Branch: slaclab/ignore-bd-tcl

Notes:

Description

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Major Release

21 Nov 22:50
@ruck314 ruck314
v2.0.0
3aec350
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Major Release

Pull Requests

  1. #561 - v2.0.0 release candidate
  2. #541 - ESCORE-335: Refactor all VHDL files and ruckus scripts to use surf as a library
  3. #543 - Updating the generics for inferred memory declaration
  4. #560 - Remaining work lib leftovers
  5. #564 - Update Headers
  6. #552 - Gearbox and Scrambler: Bit Reversal Generics
  7. #556 - VHDL lib bug fix for GigEthLvdsUltraScale.vhd using SaltUltraScaleCore.dcp
  8. #554 - MEMORY_TYPE_G fixes
  9. #553 - ClkRst.vhd: clock period rounding error bug fix
  10. #555 - bug fix for adding protocols/xvc-udp to surf lib
  11. #559 - Misc fw lib bug fixes
  12. #563 - removing remaining USE_BUILT_IN_G and XIL_DEVICE_G
  13. #558 - bug fix for repeated MEMORY_TYPE_G generic in SsiPrbsRx.vhd

Pull Request Details

v2.0.0 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Nov 21 14:46:49 2019 -0800
Pull: #561 (5745 additions, 7351 deletions, 797 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Refactor all VHDL files and ruckus scripts to use surf as a library #541
    • Which WILL break existing builds when upgrading
  • Depreciated the following generics used in FIFOs and BRAMs (which may breaks existing builds when upgrading) #543
    • BRAM_EN_G (use MEMORY_TYPE_G instead)
    • USE_DSP48_G (remove from code when upgrading)
    • ALTERA_SYN_G (use MEMORY_TYPE_G="altera_mf" instead)
    • ALTERA_RAM_G (use MEMORY_TYPE_G="altera_mf" instead)
    • USE_BUILT_IN_G (use MEMORY_TYPE_G="xpm" instead)
    • XIL_DEVICE_G (use MEMORY_TYPE_G="xpm" instead)
  • ClkRst.vhd: clock period rounding error bug fix #553
  • Gearbox and Scrambler: Bit Reversal Generics #552
  • MEMORY_TYPE_G fixes #554
  • VHDL lib bug fix for GigEthLvdsUltraScale.vhd using SaltUltraScaleCore.dcp #556
  • bug fix for adding protocols/xvc-udp to surf lib #555
  • bug fix for repeated MEMORY_TYPE_G generic in SsiPrbsRx.vhd #558
  • Misc fw lib bug fixes #559
  • Remaining work lib leftovers #560

ESCORE-335: Refactor all VHDL files and ruckus scripts to use surf as a library
Author: Benjamin Reese [email protected]
Date: Mon Nov 18 14:43:34 2019 -0800
Pull: #541 (5133 additions, 3497 deletions, 782 files changed)
Branch: slaclab/vhdl-lib

Notes:

Description

  • Refactor SURF from to use a surf library rather than dumping everything in work
  • This prevent namespace conflicts that we are starting to see with other firmware libraries

Details

I've written an explainer for how to refactor your code for these changes:
https://github.com/slaclab/surf/wiki/Refactoring-for-VHDL-Libraries

JIRA

https://jira.slac.stanford.edu/browse/ESCORE-169

Related

#335
This is a recreation of #525. I wanted to change the branch name for consistency across all of our libraries.

Updating the generics for inferred memory declaration
Author: Benjamin Reese [email protected]
Date: Mon Nov 18 15:04:18 2019 -0800
Pull: #543 (512 additions, 1832 deletions, 124 files changed)
Branch: slaclab/BRAM_EN_G-to-MEMORY_TYPE_G

Notes:

Description

  • All RAM related modules (including FIFOs) now use the MEMORY_TYPE_G generic instead of BRAM_EN_G.
  • This will break existing builds
  • Adds support to make URAM with inferred RTL (instead of XPM)
  • depreciated ALTERA_SYN_G and ALTERA_RAM_G
  • depreciated FifoAsyncBuiltIn and FifoSyncBuiltIn
  • removed USE_DSP48_G from all FIFOs
  • renaming USE_DSP48_G to USE_DSP_G
    image

Remaining work lib leftovers
Author: Benjamin Reese [email protected]
Date: Thu Nov 21 11:45:44 2019 -0800
Pull: #560 (19 additions, 1409 deletions, 17 files changed)
Branch: slaclab/remaining-work-lib-leftovers

Notes:

Description

  • Resolving the last remaining work lib dependence in SURF
    • SURF should have zero dependence on VHDL work library

Update Headers
Author: Larry Ruckman [email protected]
Date: Thu Nov 21 14:01:14 2019 -0800
Pull: #564 (0 additions, 654 deletions, 654 files changed)
Branch: slaclab/update-header

Notes:

Description

Remove the -- File: line in every VHDL header. It is useless.

Gearbox and Scrambler: Bit Reversal Generics
Author: Larry Ruckman [email protected]
Date: Mon Nov 18 15:12:22 2019 -0800
Pull: #552 (112 additions, 35 deletions, 4 files changed)
Branch: slaclab/Gearbox

Notes:

Description

VHDL lib bug fix for GigEthLvdsUltraScale.vhd using SaltUltraScaleCore.dcp
Author: Larry Ruckman [email protected]
Date: Wed Nov 20 09:36:32 2019 -0800
Pull: #556 (43 additions, 1 deletions, 2 files changed)
Branch: slaclab/GigEthLvdsUltraScale-vhdl-lib

Notes:

Description

  • VHDL lib bug fix for GigEthLvdsUltraScale.vhd using SaltUltraScaleCore.dcp
  • adding .vho to .gitignore

MEMORY_TYPE_G fixes
Author: Larry Ruckman [email protected]
Date: Tue Nov 19 14:08:41 2019 -0800
Pull: #554 (6 additions, 11 deletions, 5 files changed)
Branch: slaclab/memory_type_g-fixes

Notes:

Description

  • Bug fixes for the PR #543 merge

ClkRst.vhd: clock period rounding error bug fix
Author: Larry Ruckman [email protected]
Date: Mon Nov 18 15:12:13 2019 -0800
Pull: #553 (14 additions, 2 deletions, 1 files changed)
Branch: slaclab/ESCORE-501
Jira: https://jira.slac.stanford.edu/issues/ESCORE-501

Notes:

Description

  • Before this PR with a simulation of 1 ps time resolution, the refClk320 would have a period of 3.124 ps
   U_refClk320 : entity work.ClkRst
      generic map (
         CLK_PERIOD_G      => 3.125 ns,  -- 320 MHz
         RST_START_DELAY_G => 0 ns,
         RST_HOLD_TIME_G   => 100 us)
      port map (
         clkP => refClk320,
         rst  => usrRst);
  • This PR fixes this issue by having non-50% duty cycle of the clock period instead of rounding error

bug fix for adding protocols/xvc-udp to surf lib
Author: Larry Ruckman [email protected]
Date: Wed Nov 20 09:38:16 2019 -0800
Pull: #555 (4 additions, 4 deletions, 2 files changed)
Branch: slaclab/xvc-udp

Notes:

Description

  • bug fix for adding protocols/xvc-udp to surf lib
  • Didn't get added during the refactoring process
    • Probably last minute add without running the refactoring script

Misc fw lib bug fixes
Author: Larry Ruckman [email protected]
Date: Wed Nov 20 15:03:46 2019 -0800
Pull: #559 (5 additions, 2 deletions, 3 files changed)
Branch: slaclab/misc-fw-lib-bug-fixes

Notes:

Description

  • VHDL FW lib refactoring bug fix
  • bug fix for switching from NUMERIC_STD to std_logic_unsigned/std_logic_arith
  • updating GigEthGtp7Wrapper.AXIS_CONFIG_G default
    • make it the same as the other ETH modules

removing remaining USE_BUILT_IN_G and XIL_DEVICE_G
Author: Larry Ruckman [email protected]
Date: Thu Nov 21 12:31:30 2019 -0800
Pull: #563 (0 additions, 2 deletions, 1 files changed)
Branch: slaclab/Fifo-USE_BUILT_IN_G

Notes:

Description

  • Found 1 last USE_BUILT_IN_G and XIL_DEVICE_G in Fifo.vhd

bug fix for repeated MEMORY_TYPE_G generic in SsiPrbsRx.vhd
Author: Larry Ruckman [email protected]
Date: Wed Nov 20 11:37:48 2019 -0800
Pull: #558 (0 additions, 2 deletions, 1 files changed)
Branch: slaclab/SsiPrbsRx-bug-fix

Notes:

Description

  • bug fix for repea...
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Minor Release

14 Nov 19:31
@ruck314 ruck314
v1.12.0
bd64bbc
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Minor Release

Pull Requests

  1. #551 - v1.12.0 release candidate
  2. #537 - adding current autoneg values to RSSI AXI-Lite interface
  3. #549 - Add XVC-UDP JTAG Bridge
  4. #550 - Adding Idelaye3Wrapper and Odelaye3Wrapper module
  5. #536 - Adding AxiStreamCombiner.vhd and AxiStreamSplitter.vhd
  6. #540 - adding support for Si5345 boot ROM and added Pca9506.py
  7. #526 - Miscellaneous fixes from TACS development
  8. #535 - Add AxiLiteMasterProxy Module
  9. #524 - Rogue reorg
  10. #539 - Adding generic one-shot module
  11. #521 - Updates to Inferred FIFOs and JESD Bus Converters
  12. #529 - adding mw-master's AxiLiteRingBuffer.py
  13. #522 - Remove Xilinx library dependencies from generic modules
  14. #538 - bug fix for rssi autoneg
  15. #528 - adding PIPELINE generics to SsiInsertSof
  16. #530 - PGPv3: Adding user resetTx feature
  17. #546 - Update README.md
  18. #548 - AxiVersion.py: prevent rogue crash when timeout on buildStamp register transaction
  19. #527 - resolving ieee.numeric_std v.s. ieee.std_logic_unsigned conflicts
  20. #547 - Updating AxiVersion.UpTime parser
  21. #544 - Update JesdTestStreamTx.vhd
  22. #520 - reorganization of axi/dma/
  23. #519 - Remove USE_DSP48_G generic that was deprecated in SyncTrigRate module

Pull Request Details

v1.12.0 release candidate
Author: Larry Ruckman [email protected]
Date: Thu Nov 14 11:29:00 2019 -0800
Pull: #551 (3531 additions, 1032 deletions, 106 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Remove USE_DSP48_G generic that was deprecated in SyncTrigRate module #519
  • reorganization of axi/dma/ #520
  • Remove Xilinx library dependencies from generic modules #522
  • resolving ieee.numeric_std v.s. ieee.std_logic_unsigned conflicts #527
  • Miscellaneous fixes from TACS development #526
  • Updates to Inferred FIFOs and JESD Bus Converters #521
  • Rogue reorg #524
  • adding mw-master's AxiLiteRingBuffer.py #529
  • Adding AxiStreamCombiner.vhd and AxiStreamSplitter.vhd #536
  • adding PIPELINE generics to SsiInsertSof #528
  • PGPv3: Adding user resetTx feature #530
  • adding current autoneg values to RSSI AXI-Lite interface #537
  • bug fix for rssi autoneg #538
  • adding support for Si5345 boot ROM and added Pca9506.py #540
  • Update JesdTestStreamTx.vhd #544
  • Adding generic one-shot module #539
  • Updating AxiVersion.UpTime parser #547
  • AxiVersion.py: prevent rogue crash when timeout on buildStamp register transaction #548
  • Add AxiLiteMasterProxy Module #535
  • Add XVC-UDP JTAG Bridge #549
  • Adding Idelaye3Wrapper and Odelaye3Wrapper module #550
  • Update README.md #546

adding current autoneg values to RSSI AXI-Lite interface
Author: Larry Ruckman [email protected]
Date: Fri Oct 25 09:51:02 2019 -0700
Pull: #537 (712 additions, 713 deletions, 5 files changed)
Branch: slaclab/ESCORE-445
Jira: https://jira.slac.stanford.edu/issues/ESCORE-445

Notes:

Description

  • Add current autoneg values to RSSI AXI-Lite interface
  • Redo synchronization
    • Previous version used a HUGE amount of LUTRAM for clock synchronization of configuration registers that 99.9% of the time never change.
    • And if changed, it’s a “set and forget” type of configuration.
    • Therefore we can get away with SynchronizerVector instead of SynchronizerFifo.
    • This will help minimize the resource requirements on small FPGAs like Artix-7.

Add XVC-UDP JTAG Bridge
Author: Larry Ruckman [email protected]
Date: Thu Nov 14 08:27:23 2019 -0800
Pull: #549 (930 additions, 0 deletions, 29 files changed)
Branch: slaclab/udp-jtag-bridge

Notes:

Description

This PR adds a UDP bridge for the Xilinx XVC protocol. This used to live in it's own repository at https://github.com/slaclab/xvc-udp-debug-bridge, but it made sense to merge it in to SURF.

Details

I was unfortunately unable to preserve the history from the old repository. Git LFS messes it all up.

JIRA

Related

Adding Idelaye3Wrapper and Odelaye3Wrapper module
Author: Larry Ruckman [email protected]
Date: Thu Nov 14 10:26:13 2019 -0800
Pull: #550 (395 additions, 0 deletions, 3 files changed)
Branch: slaclab/Delaye3PatchFsm

Notes:

Description

Adding AxiStreamCombiner.vhd and AxiStreamSplitter.vhd
Author: Larry Ruckman [email protected]
Date: Wed Oct 23 16:50:54 2019 -0700
Pull: #536 (382 additions, 0 deletions, 2 files changed)
Branch: slaclab/mw-master-Combiner-Splitter

Notes:

Description

  • Adding AxiStreamCombiner.vhd and AxiStreamSplitter.vhd

adding support for Si5345 boot ROM and added Pca9506.py
Author: Larry Ruckman [email protected]
Date: Thu Oct 31 10:00:08 2019 -0700
Pull: #540 (235 additions, 10 deletions, 4 files changed)
Branch: slaclab/Si5345-boot-rom

Notes:

Description

  • adding support for Si5345 boot ROM
    • Stores the .mem into a BRAM
  • adding Si5345 .csv-to-.mem converter script
  • adding surf.devices.nxp.Pca9506.py

Miscellaneous fixes from TACS development
Author: Benjamin Reese [email protected]
Date: Tue Oct 22 13:58:17 2019 -0700
Pull: #526 (133 additions, 107 deletions, 2 files changed)
Branch: slaclab/tacs-dev

Notes:

Description

This will merge in some changes made while developing the TACS project.

  • GigEthGtp7Wrapper
    • Add a SIMULATION_G generic
    • Allow selection of DIV2 refclk and output GT clocks
  • Fix SpiSlave bug that would appear of CPHA_G='1'

Details

The clocking changes to GigEthGtp7Wrapper will break a few instantiations, but the affected projects all belong to me and I will change them as necessary.

Add AxiLiteMasterProxy Module
Author: Larry Ruckman [email protected]
Date: Tue Nov 12 13:14:27 2019 -0800
Pull: #535 (166 additions, 0 deletions, 1 files changed)
Branch: slaclab/mw-master-AxiLiteMasterProxy

Notes:

Description

  • adding AxiLiteMasterProxy.vhd

Rogue reorg
Author: Larry Ruckman [email protected]
Date: Wed Oct 23 13:05:26 2019 -0700
Pull: #524 (138 additions, 11 deletions, 3 files changed)
Branch: slaclab/rogue-reorg

Notes:

Updates needed to move to Rogue v4

Description

The _Adc32Rf45 device produces memory overlap due to the pretense of the rawWrite method calls. So, we need to use overlapEn = True in its registers.

Adding generic one-shot module
Author: Larry Ruckman [email protected]
Date: Thu Nov 7 10:59:24 2019 -0800
Pull: #539 (138 additions, 0 deletions, 1 files changed)
Branch: slaclab/ProgOneShot

Notes:

Description

  • Similar to SynchronizerOneShot.vhd but does not include Synchronizer and supports programmable pulse width outputs

Updates to Inferred FIFOs and JESD Bus Converters
Author: Larry Ruckman [email protected]
Date: Tue Oct 22 18:06:10 2019 -0700
Pull: #521 (72 additions, 58 deletions, 7 files changed)
Branch: slaclab/ESCORE-484
Jira: https://jira.slac.stanford.edu/issues/ESCORE-484

Notes:

Description

  • optimizing for resources and timing for LUTRAM inferred FIFOs
  • updating rdEn from combinatoric output to registered output for JESD bus downconverters
  • bug fix in FifoRdFsm.vhd (related to rdIndex pointer)
  • adding comments to code to DualPortRam.vhd

adding mw-master's AxiLiteRingBuffer.py
Author: Larry Ruckman [email protected]
Date: Wed Oct 23 16:50:15 2019 -0700
Pull: #529 (106 additions, 0 deletions, 2 files changed)
Branch: slaclab/AxiLiteRingBuffer-py

Notes:

Description

  • adding mw-master's AxiLiteRingBuffer.p...
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Minor Release

20 Oct 23:30
@ruck314 ruck314
v1.11.0
09490ac
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Minor Release

Pull Requests

  1. #518 - v1.11.0 release candidate
  2. #507 - Caui4 Update: Adding FEC support via harden IP
  3. #516 - Update _Lmk04828.py
  4. #497 - resolving memory overlaps and incomplete enum issues
  5. #496 - AxiStreamMon Overhaul
  6. #512 - deprecating JesdSysrefDly.vhd and increasing sysref delay sweep max from 32 to 256 cycles
  7. #506 - adding external clock support for Ultrascale GTH GbE and XAUI
  8. #509 - Adding transition frame support to AxiStreamBatcherEventBuilder
  9. #503 - adding GEN_ASYNC_G generic to Jesd204bRx.vhd and Jesd204bTx.vhd
  10. #498 - encoding a "PGPv2b-like" locData/remData into the unused 56-bit skip code payload
  11. #511 - adding SYNTH_MODE_G to all JESD bus width converters
  12. #502 - adding multiple JesdTx sync support
  13. #505 - adding AxiI2cRegMaster select bus
  14. #517 - Travis: Python byte-compile for python syntaxing checking
  15. #513 - Change FifoAsync -> Fifo with appropriate generics.
  16. #504 - Adding common AxiStreamOctal types
  17. #495 - pyrogue: array slicing bug fix
  18. #510 - Jesd204bTb: fix broken interface
  19. #508 - Updated Adc32Rf45 to only be controlled by LMK SYSREF
  20. #493 - Typo fix
  21. #500 - performance optimization for SyncMinMax.vhd
  22. #499 - Resolved i2cRegSlave.sv bug
  23. #501 - bug fix for JesdTx.py
  24. #494 - Pgp3 gth us+ bug fix

Pull Request Details

v1.11.0 release candidate
Author: Larry Ruckman [email protected]
Date: Sun Oct 20 16:28:07 2019 -0700
Pull: #518 (3062 additions, 3879 deletions, 55 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Typo fix #493
  • Pgp3 gth us+ bug fix #494
  • pyrogue: array slicing bug fix #495
  • resolving memory overlaps and incomplete enum issues #497
  • AxiStreamMon Overhaul #496
  • performance optimization for SyncMinMax.vhd #500
  • bug fix for JesdTx.py #501
  • adding multiple JesdTx sync support #502
  • Resolved i2cRegSlave.sv bug #499
  • Adding common AxiStreamOctal types #504
  • adding AxiI2cRegMaster select bus #505
  • Caui4 Update: Adding FEC support via harden IP #507
  • adding external clock support for Ultrascale GTH GbE and XAUI #506
  • encoding a "PGPv2b-like" locData/remData into the unused 56-bit skip code payload #498
  • Updated Adc32Rf45 to only be controlled by LMK SYSREF #508
  • Adding transition frame support to AxiStreamBatcherEventBuilder #509
  • adding SYNTH_MODE_G to all JESD bus width converters #511
  • deprecating JesdSysrefDly.vhd and increasing sysref delay sweep max from 32 to 256 cycles #512
  • Jesd204bTb: fix broken interface #510
  • Change FifoAsync -> Fifo with appropriate generics. #513
  • Update _Lmk04828.py #516
  • Travis: Python byte-compile for python syntaxing checking #517

Caui4 Update: Adding FEC support via harden IP
Author: Larry Ruckman [email protected]
Date: Thu Oct 10 09:57:22 2019 -0700
Pull: #507 (902 additions, 812 deletions, 5 files changed)
Branch: slaclab/ESCORE-480
Jira: https://jira.slac.stanford.edu/issues/ESCORE-480

Notes:

Description

  • adding FEC support via harden IP

Update _Lmk04828.py
Author: Larry Ruckman [email protected]
Date: Fri Oct 18 09:02:39 2019 -0700
Pull: #516 (751 additions, 921 deletions, 1 files changed)
Branch: slaclab/LMK-python-update

Notes:

Description

  1. Changed description = "LMK Registers" to actual descriptions of the registers
  2. Changing the bitOffset to match the register name with a barrel shift of 2
  3. Adding Fixed Register sets into the init() function
  4. Reorg the register order to match the data sheet (excluding the aliased registers)

Testing

  • In my Generic AMC testing, this fixed the issue where doing ReadAll on the LMK SPI would cause the SYSREF to fluctuate (SysRefPeriodMin != SysRefPeriodMax) and lose JesdRx links

resolving memory overlaps and incomplete enum issues
Author: Larry Ruckman [email protected]
Date: Fri Sep 27 08:22:12 2019 -0700
Pull: #497 (336 additions, 1244 deletions, 1 files changed)
Branch: slaclab/ESCORE-380
Jira: https://jira.slac.stanford.edu/issues/ESCORE-380

Notes:

Description

  • resolving memory overlaps and incomplete enum issues

AxiStreamMon Overhaul
Author: Larry Ruckman [email protected]
Date: Fri Sep 27 13:23:36 2019 -0700
Pull: #496 (329 additions, 313 deletions, 6 files changed)
Branch: slaclab/AxiStreamMonAxiL-logic-optimization

Notes:

Description

  • Adding frameCnt register
  • Replacing the redundant min/max logic with the common SyncMinMax.vhd module
  • Using AxiDualPortRam for AXI-Lite address decode
    • Help with making timing when AXIS_NUM_SLOTS_G is large
  • For AxiStreamMonAxiL, using AxiDualPortRam as the one module for clock crossing
    • Instead of the many LUTRAM (SynchronizerFifo) in the submodule
    • Note: SynchronizerFifo optimizes away if SynchronizerFifo.COMMON_CLK_G = true
  • Implementing the SyncMinMax with DSP48 primitives

deprecating JesdSysrefDly.vhd and increasing sysref delay sweep max from 32 to 256 cycles
Author: Larry Ruckman [email protected]
Date: Wed Oct 16 14:52:18 2019 -0700
Pull: #512 (212 additions, 302 deletions, 9 files changed)
Branch: slaclab/JesdSysrefDly-replacement

Notes:

Description

  • Deprecating JesdSysrefDly.vhd and replacing it with base/general/rtl/SlvDelay.vhd
  • Increasing sysref delay sweep max from 32 to 256 cycles

adding external clock support for Ultrascale GTH GbE and XAUI
Author: Larry Ruckman [email protected]
Date: Thu Oct 10 15:21:17 2019 -0700
Pull: #506 (148 additions, 100 deletions, 4 files changed)
Branch: slaclab/ultra-gth-eth-ext-clk

Notes:

Description

  • adding external clock support for Ultrascale GTH GbE and XAUI

Adding transition frame support to AxiStreamBatcherEventBuilder
Author: Larry Ruckman [email protected]
Date: Wed Oct 16 08:44:33 2019 -0700
Pull: #509 (98 additions, 32 deletions, 2 files changed)
Branch: slaclab/EVENT-BUILD-TRANS-TDEST

Notes:

Description

  • Adding transition frame support to AxiStreamBatcherEventBuilder

adding GEN_ASYNC_G generic to Jesd204bRx.vhd and Jesd204bTx.vhd
Author: Larry Ruckman [email protected]
Date: Sun Oct 20 09:19:23 2019 -0700
Pull: #503 (73 additions, 28 deletions, 3 files changed)
Branch: slaclab/ESCRYODET-401
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-401

Notes:

Description

  • adding GEN_ASYNC_G generic to Jesd204bRx.vhd and Jesd204bTx.vhd

encoding a "PGPv2b-like" locData/remData into the unused 56-bit skip code payload
Author: Larry Ruckman [email protected]
Date: Thu Oct 10 15:28:20 2019 -0700
Pull: #498 (77 additions, 18 deletions, 6 files changed)
Branch: slaclab/ESCORE-397
Jira: https://jira.slac.stanford.edu/issues/ESCORE-397

Notes:

Description

  • encoding a PGPv2b-like locData/remData into the unused 56-bit skip code payload

adding SYNTH_MODE_G to all JESD bus width converters
Author: Larry Ruckman [email protected]
Date: Wed Oct 16 14:51:57 2019 -0700
Pull: #511 (50 additions, 36 deletions, 8 files changed)
Branch: slaclab/JESD-WIDTH-SYNTH_MODE_G

Notes:

Description

  • adding SYNTH_MODE_G to all JESD bus width converters

adding multiple JesdTx sync support
Author: Larry Ruckman [email protected]
Date: Thu Oct 3 09:15:10 2019 -0700
Pull: #502 (30 additions, 39 deletions, 1 files changed)
Branch: slaclab/JesdTx-multi-sync

Notes:

Description

  • adding multiple JesdTx sync support
    • used for multiple DAC ICs with different SYNCs
  • Addresses the issue in JIRA ESCRYODET-401
  • This will break existing builds and require them to map each SYNC with respect to each TX JESD lane

adding AxiI2cRegMaster select bus
Author: Larry Ruckman [email protected]
Date: Wed Oct 9 16:36:03 2019 -0700
Pull: #505 (11 additions, 4 deletions, 2 files changed)
Branch: slaclab/AxiI2cRegMaster-select-bus

Notes:

Description

  • adding AxiI2cRegMaster select bus
    • used with I2C analog switch expanders

Travis: Python byte-compile for python syntaxing checking
Author: Larry Ruckman [email protected]
Date: Fri Oct 18 12:17:39 2019 -0700
Pull: #517 (8 additions, 4 deletions, 3 files changed)
Branch: slaclab/travis-Byte-compile-Python

Notes:

Description

  • Adding python byte-compile to the travis recipe to check for python syntax errors

Change FifoAsync -> Fifo with appropriate generics.
Author: Larry Ruckman [email protected]
Date: Thu Oct 17 08:11:55 2019 -0700
Pull: #513 (6 additions, 6 deletions, 6 files changed)
Branch: slaclab/jesd-cdc-fifo-fix

Notes:

Description

  • Will generate FifoAsync under the hood

Adding common AxiStreamOctal types
Author: Larry Ruckma...
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