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Minor Release v2.6.0

15 Jun 20:22
@ruck314 ruck314
v2.6.0
be45f97
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Minor Release v2.6.0

Pull Requests Since v2.5.1

Unlabeled

  1. #688 - Release Candidate v2.6.0
  2. #681 - SSP Decoders Development Updates
  3. #678 - adding SelectIoRxGearboxAligner
  4. #686 - Delete SaciSlave2.vhd
  5. #687 - connecting the AXI-Lite responses
  6. #680 - Update Code10b12bPkg.vhd
  7. #684 - Add interrupt holdoff to AxiStreamDmaV2Desc
  8. #679 - Update _Dac38J84.py
  9. #685 - Update JesdRxReg.vhd
  10. #683 - Update _ClinkSerialRx.py
  11. #682 - protocols/xvc-udp/ruckus.tcl update

Pull Request Details

adding SelectIoRxGearboxAligner
Author: Larry Ruckman [email protected]
Date: Thu Jun 4 10:06:55 2020 -0700
Pull: #678 (375 additions, 0 deletions, 1 files changed)
Branch: slaclab/auto-gearbox-align

Notes:

Description

  • Adding SelectIoRxGearboxAligner

Update _Dac38J84.py
Author: Larry Ruckman [email protected]
Date: Mon Jun 8 09:53:35 2020 -0700
Pull: #679 (15 additions, 0 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-667
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-667

Notes:

Description

-- Adding NcoSync() command

Update Code10b12bPkg.vhd
Author: Larry Ruckman [email protected]
Date: Mon Jun 15 10:10:38 2020 -0700
Pull: #680 (28 additions, 7 deletions, 1 files changed)
Branch: slaclab/Code10b12bPkg

Notes:

Description

  • Adding more control symbols constants

SSP Decoders Development Updates
Author: Larry Ruckman [email protected]
Date: Mon Jun 15 12:07:23 2020 -0700
Pull: #681 (1797 additions, 105 deletions, 16 files changed)
Branch: slaclab/ssp-decoders

Notes:

Description

  • Added errorOut to SspDecoders
  • Added dispErrIn to SspDeframer.vhd
  • Added linkOutOfSync to SelectIoRxGearboxAligner for gearbox alignment
  • Added SelectioDeser for 7-series and Ultrascale+
  • Added SspDecoderLane
    • Supports 10b12b, 12b14b and 16b20b decoding

protocols/xvc-udp/ruckus.tcl update
Author: Larry Ruckman [email protected]
Date: Fri Jun 12 16:05:45 2020 -0700
Pull: #682 (0 additions, 2 deletions, 1 files changed)
Branch: slaclab/2020-dev

Notes:

Description

  • cannot add .DCP as global with Vivado 2020.1 DFX or with use IP Integrator + custom RTL modules

Update _ClinkSerialRx.py
Author: Larry Ruckman [email protected]
Date: Tue Jun 9 15:40:44 2020 -0700
Pull: #683 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/ClinkSerialRx

Notes:

Description

  • Adding method for detecting response by setting _last to None before sending followed by polling for a value of _last.

Add interrupt holdoff to AxiStreamDmaV2Desc
Author: Ryan Herbst [email protected]
Date: Fri Jun 12 14:02:17 2020 -0700
Pull: #684 (16 additions, 3 deletions, 1 files changed)
Branch: slaclab/dma-interrupt-holdoff

Notes:

Description

Added an interrupt holdoff to delay interrupts for a programmable period after interrupts are re-enabled. This prevents high rate interrupts from monopolizing the processor. Requires support in aes-stream-driver for setting holdoff period, typically done via a command-line parameter to the driver.

Update JesdRxReg.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jun 12 16:05:29 2020 -0700
Pull: #685 (4 additions, 4 deletions, 2 files changed)
Branch: slaclab/Jesd-Reg

Notes:

Description

  • Connecting axilWriteResp to axiSlaveWriteResponse()
  • Connecting axilReadResp to axiSlaveReadResponse()

Delete SaciSlave2.vhd
Author: Larry Ruckman [email protected]
Date: Fri Jun 12 16:05:12 2020 -0700
Pull: #686 (0 additions, 166 deletions, 1 files changed)
Branch: slaclab/saci-update

Notes:

Description

  • Removing SaciSlave2 because identical to SaciSlave

connecting the AXI-Lite responses
Author: Larry Ruckman [email protected]
Date: Mon Jun 15 12:08:33 2020 -0700
Pull: #687 (41 additions, 33 deletions, 5 files changed)
Branch: slaclab/rssi-reg

Notes:

Description

  • Connecting axilWriteResp to axiSlaveWriteResponse()
  • Connecting axilReadResp to axiSlaveReadResponse()

Release Candidate v2.6.0
Author: Larry Ruckman [email protected]
Date: Mon Jun 15 13:13:23 2020 -0700
Pull: #688 (2256 additions, 300 deletions, 29 files changed)
Branch: slaclab/pre-release
Issues: #678, #679, #683, #684, #681, #680, #685, #686, #682, #687

Notes:

New Features

  • adding SelectIoRxGearboxAligner #678
  • Update _Dac38J84.py #679
  • Update _ClinkSerialRx.py #683
  • Add interrupt holdoff to AxiStreamDmaV2Desc #684
  • SSP Decoders Development Updates #681
  • Update Code10b12bPkg.vhd #680

Bug Fixes

  • Update JesdRxReg.vhd #685
  • Delete SaciSlave2.vhd #686
  • protocols/xvc-udp/ruckus.tcl update #682
  • connecting the AXI-Lite responses #687
Assets 2
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Patch Release v2.5.1

29 May 20:11
@ruck314 ruck314
v2.5.1
5cbe2c5
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Patch Release v2.5.1

Pull Requests Since v2.5.0

Unlabeled

  1. #677 - Release Candidate v2.5.1
  2. #674 - Update SlvDelayFifo.vhd
  3. #670 - Ti ADC Pyrogue Verify Cleanup
  4. #676 - Travis CI Upgrade to dist=focal (Ubuntu 20.04)
  5. #675 - Fix SlvDelayFifo Syntax to Allow VCS Compilation
  6. #671 - Si5345Lite.LoadCsvFile() Update
  7. #672 - Fix SspFramer

Pull Request Details

Ti ADC Pyrogue Verify Cleanup
Author: Larry Ruckman [email protected]
Date: Fri May 29 12:37:32 2020 -0700
Pull: #670 (5 additions, 71 deletions, 3 files changed)
Branch: slaclab/ESCORE-561
Jira: https://jira.slac.stanford.edu/issues/ESCORE-561

Notes:

Description

  • python/surf/devices/ti/_Adc16Dx370.py: removed unused verify arg
  • python/surf/devices/ti/_Ads54J60.py: removed verify arg
  • python/surf/devices/ti/_Ads54J60Channel.py: removed verify arg

Si5345Lite.LoadCsvFile() Update
Author: Larry Ruckman [email protected]
Date: Wed May 27 08:27:44 2020 -0700
Pull: #671 (7 additions, 2 deletions, 1 files changed)
Branch: slaclab/Si5345Lite-update

Notes:

Description

  • Added .csv file extension checking to Si5345Lite.LoadCsvFile()

Fix SspFramer
Author: Larry Ruckman [email protected]
Date: Fri May 29 12:37:06 2020 -0700
Pull: #672 (1 additions, 0 deletions, 1 files changed)
Branch: slaclab/fixSspFramer

Notes:

Description

  • if only 1 WORD was sent in a frame, data is lost. Back-pressure on EOF fixes that.

Update SlvDelayFifo.vhd
Author: Larry Ruckman [email protected]
Date: Thu May 28 08:40:24 2020 -0700
Pull: #674 (64 additions, 46 deletions, 1 files changed)
Branch: slaclab/ESCORE-563
Issues: #674
Jira: https://jira.slac.stanford.edu/issues/ESCORE-563

Notes:

Description

  • combined the data/delay FIFOs together
    • more logic efficient and less resources
  • Prevent delay configurations less than min FIFO latency from being used in readoutTime calculation
  • Added error checking of DELAY_BITS_G with respect to min FIFO latency
  • Using = instead of <= for fifoReadoutTime versus r.timeNow because of bug in the r.timeNow roll over case
  • Using combinatorial output (instead of registered output) for the FIFO's read enable to support 100% FIFO write duty cycles
    • Resolve the issue of lossing data if FIFO writes are more 50% for a long period of time
    • Resolve the issue of two back-to-back FIFO writes and holding off until timeNow roll over to recover of the 2nd read being behind in time
  • Added optional inputAFull for possible flow control

Fix SlvDelayFifo Syntax to Allow VCS Compilation
Author: Benjamin Reese [email protected]
Date: Thu May 28 10:34:37 2020 -0700
Pull: #675 (19 additions, 12 deletions, 1 files changed)
Branch: slaclab/SlvDelayFifo-vcs

Notes:

Description

Fix VHDL syntax so that SlvDelayFifo will compile in VCS.

Details

VCS is really pedantic and raised the following errors:

Parsing design file '/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd'
Error-[LOADEXPRFNAMENOTSTATIC] Illegal parameter association
/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd, 102
RTL
           din(DATA_FIELD_C)   => inputData,
              ^
  The formal part of association element must be a locally static name.
  Please refer to section 6.1 of the VHDL93 LRM for details about locally 
  static name.
Error-[LOADEXPRFNAMENOTSTATIC] Illegal parameter association
/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd, 103
RTL
           din(DELAY_FIELD_C)  => r.readoutTime,
              ^
  The formal part of association element must be a locally static name.
  Please refer to section 6.1 of the VHDL93 LRM for details about locally 
  static name.
Error-[LOADEXPRFNAMENOTSTATIC] Illegal parameter association
/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd, 107
RTL
           dout(DATA_FIELD_C)  => fifoReadoutData,
               ^
  The formal part of association element must be a locally static name.
  Please refer to section 6.1 of the VHDL93 LRM for details about locally 
  static name.
Error-[LOADEXPRFNAMENOTSTATIC] Illegal parameter association
/u/re/bareese/projects/lcls2-timetool/firmware/submodules/surf/base/general/rtl/SlvDelayFifo.vhd, 108
RTL
           dout(DELAY_FIELD_C) => fifoReadoutTime,
               ^
  The formal part of association element must be a locally static name.
  Please refer to section 6.1 of the VHDL93 LRM for details about locally 
  static name.

JIRA

Related

Travis CI Upgrade to dist=focal (Ubuntu 20.04)
Author: Larry Ruckman [email protected]
Date: Fri May 29 12:37:18 2020 -0700
Pull: #676 (14 additions, 41 deletions, 3 files changed)
Branch: slaclab/travis-focal

Notes:

Description

  • Update to Ubuntu Focal (20.04)
  • Update to apt install of ghdl
    • now part of default package manger for 20.04
  • Delete ghdl-travis-install.sh
  • Resolving python linter error

Release Candidate v2.5.1
Author: Larry Ruckman [email protected]
Date: Fri May 29 13:07:51 2020 -0700
Pull: #677 (98 additions, 160 deletions, 9 files changed)
Branch: slaclab/pre-release
Issues: #671, #674, #675, #670, #672, #676

Notes:

Description

  • Si5345Lite.LoadCsvFile() Update #671
  • Update SlvDelayFifo.vhd #674
  • Fix SlvDelayFifo Syntax to Allow VCS Compilation #675
  • pr.Device verify cleanup #670
  • Fix SspFramer #672
  • Travis CI Upgrade to dist=focal (Ubuntu 20.04) #676
Assets 2
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Minor Release v2.5.0

18 May 18:05
@ruck314 ruck314
v2.5.0
762c432
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Minor Release v2.5.0

Pull Requests Since v2.4.0

Bug

  1. #661 - SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd

Unlabeled

  1. #669 - Release Candidate v2.5.0
  2. #663 - Add AXIL-DRP interface for GigE GTX7
  3. #665 - Adding AxiStreamResizeTb.vhd
  4. #662 - Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd
  5. #666 - Resolving double YAML load issue
  6. #664 - Add register verify for the read/write registers
  7. #667 - Update _Lmk04828.py
  8. #668 - Cache ClinkSerialRx response for reading

Pull Request Details

SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd
Author: Larry Ruckman [email protected]
Date: Thu Apr 30 16:03:38 2020 -0700
Pull: #661 (471 additions, 27 deletions, 4 files changed)
Branch: slaclab/SrpV3AxiTb
Labels: bug

Notes:

Description

  • Added SrpV3AxiTb.vhd
  • AXI stream resize bug fix for SrpV3Core.vhd
    • bug fix for when external AXIS is not 32-bit wide tData

Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd
Author: Larry Ruckman [email protected]
Date: Thu May 14 09:03:31 2020 -0700
Pull: #662 (71 additions, 31 deletions, 2 files changed)
Branch: slaclab/boxcarPipeline

Notes:

trying to address timing closure for MPS Central node. Modified BoxCarIntegrator to add register output to memory used and pipeline for processing. It is optional controlled by generic options. It is not tested yet.

Add AXIL-DRP interface for GigE GTX7
Author: Benjamin Reese [email protected]
Date: Fri May 15 22:35:15 2020 -0700
Pull: #663 (1819 additions, 78 deletions, 7 files changed)
Branch: slaclab/gtx7-drp

Notes:

Description

The GigEth GTX7 DCP core was regenerated in slaclab/surf-dcp-targets#2 to add DRP and txdiffctrl ports. This DCP has been copied into SURF. The DRP ports have been attached to an AxiLiteToDrp bridge and the TX drive strength ports brought out to top level ports.

Some minor cleanup was also done on the GigEthReg python Device class.

Details

Add register verify for the read/write registers
Author: Larry Ruckman [email protected]
Date: Wed May 13 08:53:25 2020 -0700
Pull: #664 (15 additions, 1 deletions, 1 files changed)
Branch: slaclab/ESCRYODET-652
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-652

Notes:

Description

  • Add register verify for the read/write registers to catch broken SPI interfaces

Adding AxiStreamResizeTb.vhd
Author: Larry Ruckman [email protected]
Date: Thu May 14 09:03:08 2020 -0700
Pull: #665 (292 additions, 0 deletions, 1 files changed)
Branch: slaclab/ESCORE-560
Jira: https://jira.slac.stanford.edu/issues/ESCORE-560

Notes:

Resolving double YAML load issue
Author: Larry Ruckman [email protected]
Date: Thu May 14 13:40:59 2020 -0700
Pull: #666 (60 additions, 8 deletions, 4 files changed)
Branch: slaclab/ESCRYODET-567
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-567

Notes:

Description

  • Update Init() delays in Adc32Rf45, Dac38J84 and Lmk04828

Update _Lmk04828.py
Author: Larry Ruckman [email protected]
Date: Thu May 14 20:31:36 2020 -0700
Pull: #667 (3 additions, 3 deletions, 2 files changed)
Branch: slaclab/ruck314-patch-1

Notes:

Description

  • Bug fix

Cache ClinkSerialRx response for reading
Author: Larry Ruckman [email protected]
Date: Fri May 15 19:45:12 2020 -0700
Pull: #668 (3 additions, 1 deletions, 1 files changed)
Branch: slaclab/clink_serial_read
Issues: #668

Notes:

Description

Modify _ClinkSerialRx.py to cache received response on serial link to allow read result to be retrieved.

Release Candidate v2.5.0
Author: Larry Ruckman [email protected]
Date: Mon May 18 11:02:45 2020 -0700
Pull: #669 (2734 additions, 149 deletions, 21 files changed)
Branch: slaclab/pre-release
Issues: #664, #665, #662, #666, #667, #668, #663, #661

Notes:

Description

  • Add register verify for the read/write registers #664
  • Adding AxiStreamResizeTb.vhd #665
  • Adding pipeline registers to help with timing for dsp/fixed/BoxcarIntegrator.vhd #662
  • Resolving double YAML load issue #666
  • Update _Lmk04828.py #667
  • Cache ClinkSerialRx response for reading #668
  • Add AXIL-DRP interface for GigE GTX7 #663
  • SrpV3AxiTb.vhd + bug fix to SrpV3Core.vhd #661
Assets 2
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v2.4.0

27 Apr 16:25
@ruck314 ruck314
v2.4.0
70bcfcd
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v2.4.0

Pull Requests Since v2.3.0

Unlabeled

  1. #659 - release candidate v2.4.0
  2. #657 - Adding Lmk04832 and Lmx2615 python class
  3. #654 - Separated the FSM code out of UartAxiLiteMaster.vhd
  4. #655 - Update SrpV3Axi.vhd and AXI_CONFIG_G/AXI_STREAM_CONFIG_G clean up
  5. #653 - adding Defense Grade RFSoC support and some whitespace removal
  6. #658 - AxiLiteSequencerRam Feature Update
  7. #656 - Add ID,BS,OVL serial commands for Opal

Pull Request Details

adding Defense Grade RFSoC support and some whitespace removal
Author: Larry Ruckman [email protected]
Date: Wed Apr 15 20:13:09 2020 -0700
Pull: #653 (100 additions, 87 deletions, 37 files changed)
Branch: slaclab/XQZU28DR

Notes:

Description

  • adding Defense Grade RFSoC support
  • remove whitespace on all .tcl files
  • remove whitespace on all .vhd files

Separated the FSM code out of UartAxiLiteMaster.vhd
Author: Larry Ruckman [email protected]
Date: Wed Apr 22 11:49:26 2020 -0700
Pull: #654 (363 additions, 282 deletions, 2 files changed)
Branch: slaclab/UartAxiLiteMasterFsm

Notes:

  • Useful for cases when you have a byte stream and no UART serialization
    • Example: SpaceWire endpoint

Update SrpV3Axi.vhd and AXI_CONFIG_G/AXI_STREAM_CONFIG_G clean up
Author: Larry Ruckman [email protected]
Date: Wed Apr 22 11:48:43 2020 -0700
Pull: #655 (111 additions, 123 deletions, 69 files changed)
Branch: slaclab/SrpV3Axi-update

Notes:

Description

  • Force the user to define AXI_CONFIG_G and AXI_STREAM_CONFIG_G
    • Instead of accidentally building with defaults
  • Bug fix for non-32b AXI4 transactions in SrpV3Axi
    • assumed a 4-byte AXI stream, which was mismatched to the AXI4 width

Add ID,BS,OVL serial commands for Opal
Author: Larry Ruckman [email protected]
Date: Thu Apr 16 18:18:29 2020 -0700
Pull: #656 (27 additions, 2 deletions, 1 files changed)
Branch: slaclab/UartOpal_commands

Notes:

Add ID,BS,OVL serial commands for Opal

Description

Added ID,BS,OVL serial commands to python/surf/protocols/clink/_UartOpal1000.py

Adding Lmk04832 and Lmx2615 python class
Author: Larry Ruckman [email protected]
Date: Wed Apr 22 11:48:57 2020 -0700
Pull: #657 (1869 additions, 1129 deletions, 5 files changed)
Branch: slaclab/py-ti-dev

Notes:

Description

  • Adding Lmk04832 (which is 99% the same as Lmk04828)
    • Renamed original Lmk04828 to Lmk048Base
    • Inherited Lmk04828 from Lmk048Base + some exclusive registers
    • Inherited Lmk04832 from Lmk048Base + some exclusive registers
  • Adding Lmx2615 class

AxiLiteSequencerRam Feature Update
Author: Larry Ruckman [email protected]
Date: Wed Apr 22 11:49:09 2020 -0700
Pull: #658 (47 additions, 6 deletions, 1 files changed)
Branch: slaclab/ESCORE-471
Jira: https://jira.slac.stanford.edu/issues/ESCORE-471

Notes:

Description

  • adding discrete start input signal and done output to kick off the sequence

release candidate v2.4.0
Author: Larry Ruckman [email protected]
Date: Thu Apr 23 08:25:23 2020 -0700
Pull: #659 (2517 additions, 1629 deletions, 115 files changed)
Branch: slaclab/pre-release
Issues: #653, #656, #655, #657, #658, #654

Notes:

Description

  • adding Defense Grade RFSoC support and some whitespace removal #653
  • Add ID,BS,OVL serial commands for Opal #656
  • Update SrpV3Axi.vhd and AXI_CONFIG_G/AXI_STREAM_CONFIG_G clean up #655
  • Adding Lmk04832 and Lmx2615 python class #657
  • AxiLiteSequencerRam Feature Update #658
  • Separated the FSM code out of UartAxiLiteMaster.vhd #654
Assets 2
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v2.3.0

15 Apr 15:24
@ruck314 ruck314
v2.3.0
15c7aa5
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v2.3.0

Pull Requests Since v2.2.0

Bug

  1. #649 - Fix ruckus checkout branch

Enhancement

  1. #645 - Add auto release generation

Unlabeled

  1. #652 - release candidate v2.3.0
  2. #647 - Remove whitespace
  3. #644 - Add analog devices python for LLRF
  4. #646 - Converting BoxcarIntegrator.vhd to signed
  5. #651 - Fix bad baud rate counter
  6. #650 - adding dual AXI stream types
  7. #648 - missing surf library causing VCS error

Pull Request Details

Add analog devices python for LLRF
Author: Larry Ruckman [email protected]
Date: Wed Apr 1 15:45:47 2020 -0700
Pull: #644 (325 additions, 6 deletions, 5 files changed)
Branch: slaclab/llrf-python

Notes:

Description

  • Adding AttHmc624, Ad5541 and Adt7420

Add auto release generation
Author: Larry Ruckman [email protected]
Date: Mon Apr 13 11:57:23 2020 -0700
Pull: #645 (11 additions, 1 deletions, 1 files changed)
Branch: slaclab/release_gen
Labels: enhancement

Notes:

This adds auto release generation. Once a tag is pushed the release and release notes will be auto generated.

Converting BoxcarIntegrator.vhd to signed
Author: Larry Ruckman [email protected]
Date: Tue Apr 14 11:11:20 2020 -0700
Pull: #646 (131 additions, 85 deletions, 4 files changed)
Branch: slaclab/boxcarIntSigned

Notes:

Converting BoxcarIntegrator.vhd to signed

Remove whitespace
Author: Larry Ruckman [email protected]
Date: Mon Apr 13 08:49:28 2020 -0700
Pull: #647 (9719 additions, 9719 deletions, 719 files changed)
Branch: slaclab/remove-whitespace

Notes:

Description

  • removing white space from YAML files
  • removing white space from Verilog files
  • removing white space from VHDL files

missing surf library causing VCS error
Author: Larry Ruckman [email protected]
Date: Fri Apr 10 16:06:55 2020 -0700
Pull: #648 (2 additions, 0 deletions, 1 files changed)
Branch: slaclab/ePix-dev

Notes:

Just added surf library to Gtp7AutoPhaseAligner.vhd to avoid VCS failed compilation.

Fix ruckus checkout branch
Author: Larry Ruckman [email protected]
Date: Mon Apr 13 15:01:38 2020 -0700
Pull: #649 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/release_gen
Labels: bug

Notes:

Checkout master branch for ruckus release scripts.

adding dual AXI stream types
Author: Larry Ruckman [email protected]
Date: Tue Apr 14 10:45:11 2020 -0700
Pull: #650 (6 additions, 0 deletions, 1 files changed)
Branch: slaclab/AxiStreamPkg-update

Notes:

Description

  • Useful types to have pre-defined (similar to QUAD and OCTAL types)

Fix bad baud rate counter
Author: Larry Ruckman [email protected]
Date: Tue Apr 14 08:12:14 2020 -0700
Pull: #651 (10 additions, 9 deletions, 2 files changed)
Branch: slaclab/uart_fix

Notes:

Description

The previous UART implementation did not account for the output and sample clock periods.

release candidate v2.3.0
Author: Larry Ruckman [email protected]
Date: Wed Apr 15 08:21:12 2020 -0700
Pull: #652 (10190 additions, 9816 deletions, 725 files changed)
Branch: slaclab/pre-release
Issues: #644, #648, #647, #651, #650, #646

Notes:

Description

  • Add analog devices python for LLRF #644
  • missing surf library causing VCS error #648
  • Remove whitespace #647
  • Fix bad baud rate counter #651
  • adding dual AXI stream types #650
  • Converting BoxcarIntegrator.vhd to signed #646
Assets 2
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Minor Release

27 Mar 15:18
@ruck314 ruck314
v2.2.0
ae705c7
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Minor Release

Pull Requests

  1. #639 - Add external blowoff input to AxiStreamBatcherEventBuilder
  2. #640 - SURF/ETH/DHCP: reset FSM if MAC address changes
  3. #532 - AxiStreamBytePacker bug fix
  4. #642 - prevent a MAC address = 0x0 doing a DHCP request

Pull Request Details

Add external blowoff input to AxiStreamBatcherEventBuilder
Author: Benjamin Reese [email protected]
Date: Thu Mar 26 15:18:12 2020 -0700
Pull: #639 (26 additions, 6 deletions, 2 files changed)
Branch: slaclab/asbeb-blowoff

Notes:

Description

Details

This adds an external blowoff input to the AxiStreamBatcherEventBuilder and creates a new register for viewing the external input status.

JIRA

Related

SURF/ETH/DHCP: reset FSM if MAC address changes
Author: Larry Ruckman [email protected]
Date: Tue Mar 24 15:06:34 2020 -0700
Pull: #640 (16 additions, 8 deletions, 1 files changed)
Branch: slaclab/ESCORE-547
Jira: https://jira.slac.stanford.edu/issues/ESCORE-547

Notes:

Description

  • Typically this does not in a lot of our FW builds because the MAC is in the eFUSE
  • But I discovered this race condition bug in the ATLAS ATCA Link Agg FW MAC address should potential change at boot up and have to wait > 8 hours until DHCP lease expires before getting the correct IP address.

AxiStreamBytePacker bug fix
Author: Larry Ruckman [email protected]
Date: Thu Mar 26 17:50:28 2020 -0700
Pull: #532 (1 additions, 14 deletions, 1 files changed)
Branch: slaclab/mw-master-AxiStreamBytePacker

Notes:

Description

  • Shift next to current only if nxt is not full

prevent a MAC address = 0x0 doing a DHCP request
Author: Larry Ruckman [email protected]
Date: Thu Mar 26 10:40:46 2020 -0700
Pull: #642 (5 additions, 3 deletions, 1 files changed)
Branch: slaclab/dhcp-patch

Notes:

Description

  • While MAC address = 00:00:00:00:00:00 is technically a valid Ethernet MAC address, we are using MAC = 00:00:00:00:00:00 (0x0) as an invalid MAC address in the SURF FW
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Patch Release

18 Mar 16:39
@ruck314 ruck314
v2.1.3
c4a01ef
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Patch Release

Pull Requests

  1. #638 - v2.1.3 release candidate
  2. #636 - Bug Fix for EM22xx python device
  3. #637 - AxiAds42lb69Pll.vhd: include IBUFGDS when USE_FBCLK_G = false

Pull Request Details

v2.1.3 release candidate
Author: Larry Ruckman [email protected]
Date: Wed Mar 18 09:37:03 2020 -0700
Pull: #638 (253 additions, 177 deletions, 4 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • Bug Fix for EM22xx python device #636
  • AxiAds42lb69Pll.vhd: include IBUFGDS when USE_FBCLK_G = false #637

Bug Fix for EM22xx python device
Author: Larry Ruckman [email protected]
Date: Wed Mar 11 13:52:37 2020 -0700
Pull: #636 (194 additions, 132 deletions, 3 files changed)
Branch: slaclab/ESCRYODET-614
Jira: https://jira.slac.stanford.edu/issues/ESCRYODET-614

Notes:

Description

  • bug fix for LITERAL v.s. linear data format with respect to PMbus specs
  • adding simpleDisplay arg and auto-poll for status registers to python/surf/protocols/i2c/_PMBus.py

AxiAds42lb69Pll.vhd: include IBUFGDS when USE_FBCLK_G = false
Author: Larry Ruckman [email protected]
Date: Thu Mar 12 17:24:14 2020 -0700
Pull: #637 (59 additions, 45 deletions, 1 files changed)
Branch: slaclab/wave8-ruckman

Notes:

Description

  • Resolves issue of ports being unconnected/unterminated
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Minor Release

28 Feb 00:26
@ruck314 ruck314
v2.1.0
7874053
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Minor Release

Pull Requests

  1. #617 - Flake8
  2. #627 - Refactor RELEASE_DELAY_G Generic in Synchronization Modules
  3. #622 - Clean up SynchronizerOneShot
  4. #623 - SRPv0 Updates
  5. #612 - adding 185.71 MHz refClk support to pgp3/gthUs for 10.3125 Gb/s
  6. #626 - CDC fix. Use synchornized localMac
  7. #621 - CDC patch for SynchronizerOneShotCntVector and IprogUltraScale
  8. #616 - Remove mac os from conda builds
  9. #620 - 1GbE GTP7 Simulation Bug Fix
  10. #591 - bug fix for adc32rf45
  11. #624 - Fix bug in _Xadc.py
  12. #618 - missing surf library
  13. #615 - Added missing surf library
  14. #614 - Change python package name to lower case
  15. #619 - Rename tox.ini to .flake8

Pull Request Details

Flake8
Author: Larry Ruckman [email protected]
Date: Thu Feb 20 21:16:43 2020 -0800
Pull: #617 (7255 additions, 7716 deletions, 118 files changed)
Branch: slaclab/flake8

Notes:

Description

  • Added python linter to travic CI
  • Fixed some bugs in the python code
    • Caught by the linter
  • Some misc. code header clean up
  • Remove name and description args when they don't differ from the default

Refactor RELEASE_DELAY_G Generic in Synchronization Modules
Author: Benjamin Reese [email protected]
Date: Thu Feb 27 15:14:27 2020 -0800
Pull: #627 (219 additions, 231 deletions, 8 files changed)
Branch: slaclab/release-delay-fix

Notes:

Description

The RELEASE_DELAY_G generic was either not used, not necessary, or improperly named in several modules.

Details

The RELEASE_DELAY_G generic has been modified in the following modules:

  • AxiLiteSyncStatusVector - Unused, removed.
  • SyncStatusVector - Renamed to SYNC_STAGES_G
  • SynchronizerOneShotCnt - Unnecessary, removed
  • SynchronizerOneShotCntVector - Unnecessary, removed
  • SynchronizerOneShotVector - Renamed to OUT_DELAY_G

Any modules that instantiate the affected modules above have also been refactors to reflect the changes.

JIRA

Related

Clean up SynchronizerOneShot
Author: Larry Ruckman [email protected]
Date: Thu Feb 27 08:49:13 2020 -0800
Pull: #622 (180 additions, 234 deletions, 7 files changed)
Branch: slaclab/one-shot

Notes:

Description

A code-breaking cleanup of SynchronizerOneShot.

The part that might break existing code is the removal of generics. Simply cutting them from any instantiation should fix it.

Details

  • Fixed rst input and RST_ASYNC_G generic
    • rst was not being driven to the SynchronizerEdge.
    • Pulse stretch logic did not obey RST_ASYC_G.
  • Removed RELEASE_DELAY_G generic
    • Was applied to a RstSync attached to an edge detector.
    • In that setup, the release delay of RstSync doesn't matter, since we're only looking at the edge.
  • Added OUT_DELAY_G generic
    • Allows the output pulse to be delayed by a configurable number of clock cycles.
    • Must be >= 3 because the internal SynchronizerEdge is used to do the delay.
  • Optimized pulse stretch logic
    • No longer driven by combinatorial output.
    • No more state machine. Just looks at the state of r.dataOut to determine if it should be counting.

Misc

  • Changed some SynchronizerOneShot instances to PwrUpRst which is more appropriate to use.
  • Port declaration of SynchronizerOneShotCnt and SynchronizerOneShotCntVector rearranged according to clock domains.

SRPv0 Updates
Author: Larry Ruckman [email protected]
Date: Thu Feb 27 12:14:44 2020 -0800
Pull: #623 (123 additions, 105 deletions, 7 files changed)
Branch: slaclab/SRPv0-dev

Notes:

Description

  • SsiFifo bug fix when GEN_SYNC_FIFO_G=true and SLAVE_AXI_CONFIG_G/=MASTER_AXI_CONFIG_G
  • SrpV0AxiLite code clean up
  • Updating AxiLiteSrpV0Tb.vhd to have a non-32b AXIS interface
  • Updating AxiLiteSrpV0Tb.vhd to 32-bit word addressing
  • AxiStreamMuxTb code clean up
    • Does not use SssiFifo

adding 185.71 MHz refClk support to pgp3/gthUs for 10.3125 Gb/s
Author: Larry Ruckman [email protected]
Date: Wed Feb 26 13:07:10 2020 -0800
Pull: #612 (133 additions, 34 deletions, 3 files changed)
Branch: slaclab/pgp3-gthUs-refclk

Notes:

Description

  • Required for slaclab/l2si-drp
  • Using the same Pgp3GthUsIp10G IP core as the 156.25 MHz but with different QPLL configurations

CDC fix. Use synchornized localMac
Author: Larry Ruckman [email protected]
Date: Thu Feb 27 12:10:33 2020 -0800
Pull: #626 (43 additions, 34 deletions, 6 files changed)
Branch: slaclab/cdc-patch

Notes:

Description

  • CDC fix. Use synchornized localMac

CDC patch for SynchronizerOneShotCntVector and IprogUltraScale
Author: Larry Ruckman [email protected]
Date: Thu Feb 27 08:50:08 2020 -0800
Pull: #621 (72 additions, 5 deletions, 2 files changed)
Branch: slaclab/cdc-patch

Notes:

CDC fix for SynchronizerOneShotCntVector rollOverEn and cntRst.
CDC fix for IprogUltraScale bootAddress.

Description

CDC fix for SynchronizerOneShotCntVector rollOverEn and cntRst.
SynchronizerOneShotCntVector uses SynchronizerOneShotCnt with COMMON_CLK_G => true and synchronizes the status bus outside of SynchronizerOneShotCnt but then rollOverEn and cntRst also need to be sync'd outside.

CDC fix for IprogUltraScale bootAddress
Sync bootAddress to icape2Clk

Details

JIRA

Related

Remove mac os from conda builds
Author: Larry Ruckman [email protected]
Date: Thu Feb 13 10:32:42 2020 -0800
Pull: #616 (8 additions, 8 deletions, 1 files changed)
Branch: slaclab/rem_mac

Notes:

1GbE GTP7 Simulation Bug Fix
Author: Larry Ruckman [email protected]
Date: Wed Feb 26 10:16:53 2020 -0800
Pull: #620 (3 additions, 3 deletions, 1 files changed)
Branch: slaclab/gbE-gtp7-sim-bug-fix

Notes:

Description

  • Can't have mix open/assignment bus for VCS simulation

bug fix for adc32rf45
Author: Larry Ruckman [email protected]
Date: Thu Feb 20 14:18:42 2020 -0800
Pull: #591 (2 additions, 2 deletions, 1 files changed)
Branch: slaclab/adc32rf45-patch

Notes:

Description

  • Resolves adc32rf45.vhd width mismatch #589
  • This should be tested with hardware before this PR is approved
    • SMURF is the only hardware platform that uses devices/Ti/adc32rf45/rtl/adc32rf45.vhd right now

Fix bug in _Xadc.py
Author: Benjamin Reese [email protected]
Date: Wed Feb 26 11:26:00 2020 -0800
Pull: #624 (1 additions, 1 deletions, 1 files changed)
Branch: slaclab/xadc-rogue-fix

Notes:

Add default arg to pollInterval in addPair() so it doesn't need to be specified.

Not sure how this wasn't noticed before.

missing surf library
Author: Larry Ruckman [email protected]
Date: Thu Feb 20 19:31:17 2020 -0800
Pull: #618 (2 additions, 0 deletions, 1 files ...
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Patch Release

09 Mar 19:15
@ruck314 ruck314
v2.1.2
9f3c93f
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Pull Requests

  1. #635 - v2.1.2 release candidate
  2. #632 - Enable flexible baud rate multiplier in UART
  3. #633 - adding devices.nxp.Pca9555.py
  4. #631 - surf.devices.silabs python bug fixes
  5. #634 - GigEthGtp7Wrapper: Resolved namespace conflicts

Pull Request Details

v2.1.2 release candidate
Author: Larry Ruckman [email protected]
Date: Mon Mar 9 12:11:52 2020 -0700
Pull: #635 (178 additions, 112 deletions, 9 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • surf.devices.silabs python bug fixes #631
  • adding devices.nxp.Pca9555.py #633
  • Enable flexible baud rate multiplier in UART #632
  • GigEthGtp7Wrapper: Resolved namespace conflicts #634

Enable flexible baud rate multiplier in UART
Author: Larry Ruckman [email protected]
Date: Sat Mar 7 14:14:26 2020 -0800
Pull: #632 (102 additions, 96 deletions, 4 files changed)
Branch: slaclab/flex_baud

Notes:

This enables the uart to have a flexible baud rate multiplier instead of the default 16x.

adding devices.nxp.Pca9555.py
Author: Larry Ruckman [email protected]
Date: Fri Mar 6 14:43:38 2020 -0800
Pull: #633 (60 additions, 0 deletions, 2 files changed)
Branch: slaclab/nxp-Pca9555

Notes:

Description

  • Used in ATCA Link Agg development

surf.devices.silabs python bug fixes
Author: Larry Ruckman [email protected]
Date: Tue Mar 3 17:31:57 2020 -0800
Pull: #631 (12 additions, 12 deletions, 2 files changed)
Branch: slaclab/ruckman-dev

Notes:

Description

  • Fixed broken python classes

GigEthGtp7Wrapper: Resolved namespace conflicts
Author: Larry Ruckman [email protected]
Date: Mon Mar 9 08:49:13 2020 -0700
Pull: #634 (4 additions, 4 deletions, 1 files changed)
Branch: slaclab/GigEthGtp7Wrapper-update

Notes:

Description

  • There were two refClkOut output ports being mapped
  • Changing the Copy of internal MMCM reference clock and Reset ports' names
    • From refClkOut to mmcmRefClkOut
    • From refRstOut to mmcmRefRstOut
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Patch Release

29 Feb 01:50
@ruck314 ruck314
v2.1.1
ccde696
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Patch Release

Pull Requests

  1. #630 - v2.1.1 release candidate
  2. #629 - fixed bug in PGP2b that caused reset locked up at power up
  3. #628 - fixed the broken clink python modules

Pull Request Details

v2.1.1 release candidate
Author: Larry Ruckman [email protected]
Date: Fri Feb 28 17:46:58 2020 -0800
Pull: #630 (27 additions, 30 deletions, 7 files changed)
Branch: slaclab/pre-release

Notes:

Description

  • fixed the broken clink python modules #628
  • fixed bug in PGP2b that caused reset locked up at power up #629

fixed bug in PGP2b that caused reset locked up at power up
Author: Larry Ruckman [email protected]
Date: Fri Feb 28 14:06:51 2020 -0800
Pull: #629 (17 additions, 19 deletions, 3 files changed)
Branch: slaclab/pgp-bug-fix

Notes:

Description

  • Bug created in PR #622
  • Fixes GTP7, GTH Ultrascale and GTH Ultrascale+
    • No bug in other fabric fabrics

fixed the broken clink python modules
Author: Larry Ruckman [email protected]
Date: Fri Feb 28 13:57:04 2020 -0800
Pull: #628 (10 additions, 11 deletions, 4 files changed)
Branch: slaclab/clink-dev

Notes:

Description

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