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succinctlabs · Feb 29, 2024 · cff24e6 · cff24e6
1 parent fb5c006
commit cff24e6
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diff --git a/core/src/stark/machine.rs b/core/src/stark/machine.rs
@@ -103,7 +103,6 @@ impl<SC: StarkGenericConfig> RiscvStark<SC> {
         );
 
         // Generate the trace for each chip to collect events emitted from chips with dependencies.
-        println!("generating depeendencies for each chip");
         chips.iter().for_each(|chip| {
             let mut output = ExecutionRecord::default();
             output.index = record.index;

diff --git a/tests/blake3-compress/elf/riscv32im-succinct-zkvm-elf b/tests/blake3-compress/elf/riscv32im-succinct-zkvm-elf