old hwlp arch

ArchImpl/CMakeLists.txt

@@ -42,3 +42,4 @@ ADD_SUBDIRECTORY(RV32IMACFD)
 ADD_SUBDIRECTORY(RV64IMACFD)
 ADD_SUBDIRECTORY(RV32IMACFDXCoreV)
 ADD_SUBDIRECTORY(RV32IMAFDXCoreVHwlp)
+ADD_SUBDIRECTORY(RV32IMAFDXCoreVHwlpV0)

ArchImpl/RV32IMAFDXCoreVHwlpV0/CMakeLists.txt

@@ -0,0 +1,42 @@
+# Generated on Fri, 17 Nov 2023 19:17:42 +0100.
+#
+# This file contains the CMake build info for the RV32IMAFDXCoreVHwlpV0 core architecture.
+
+PROJECT(RV32IMAFDXCoreVHwlpV0)
+
+SET(CMAKE_BUILD_WITH_INSTALL_RPATH TRUE)
+SET(CMAKE_INSTALL_RPATH "\$ORIGIN/../../include/jit/etiss/jit")
+
+ADD_LIBRARY(${PROJECT_NAME} SHARED
+	RV32IMAFDXCoreVHwlpV0Arch.cpp
+	RV32IMAFDXCoreVHwlpV0ArchLib.cpp
+	RV32IMAFDXCoreVHwlpV0ArchSpecificImp.cpp
+	RV32IMAFDXCoreVHwlpV0Instr.cpp
+	RV32IMAFDXCoreVHwlpV0_RV32IInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_RV32MInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_RV32FInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_RV32DInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_ZifenceiInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_XCoreVSimdInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_XCoreVBitmanipInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_XCoreVAluInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_XCoreVBranchImmediateInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_XCoreVMemInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_XCoreVMacInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_XCoreVHwlpV0Instr.cpp
+	RV32IMAFDXCoreVHwlpV0_tum_csrInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_tum_retInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_RV32AInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_tum_rvaInstr.cpp
+	RV32IMAFDXCoreVHwlpV0_tum_semihostingInstr.cpp
+)
+
+add_custom_command(
+	TARGET ${PROJECT_NAME} POST_BUILD
+	COMMAND ${CMAKE_COMMAND} -E copy
+		"${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h"
+		"${ETISS_BINARY_DIR}/include/jit/Arch/${PROJECT_NAME}"
+)
+INSTALL(FILES "${CMAKE_CURRENT_LIST_DIR}/${PROJECT_NAME}Funcs.h" DESTINATION "include/jit/Arch/${PROJECT_NAME}")
+
+ETISSPluginArch(${PROJECT_NAME})

ArchImpl/RV32IMAFDXCoreVHwlpV0/RV32IMAFDXCoreVHwlpV0.h

@@ -0,0 +1,77 @@
+/**
+ * Generated on Fri, 17 Nov 2023 19:17:42 +0100.
+ *
+ * This file contains the registers for the RV32IMAFDXCoreVHwlpV0 core architecture.
+ */
+
+#ifndef ETISS_RV32IMAFDXCoreVHwlpV0Arch_RV32IMAFDXCoreVHwlpV0_H_
+#define ETISS_RV32IMAFDXCoreVHwlpV0Arch_RV32IMAFDXCoreVHwlpV0_H_
+#include <stdio.h>
+#include "etiss/jit/CPU.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#pragma pack(push, 1)
+struct RV32IMAFDXCoreVHwlpV0 {
+	ETISS_CPU cpu; // original cpu struct must be defined as the first field of the new structure. this allows to cast X * to ETISS_CPU * and vice vers
+	etiss_uint32 ZERO;
+	etiss_uint32 RA;
+	etiss_uint32 SP;
+	etiss_uint32 GP;
+	etiss_uint32 TP;
+	etiss_uint32 T0;
+	etiss_uint32 T1;
+	etiss_uint32 T2;
+	etiss_uint32 S0;
+	etiss_uint32 S1;
+	etiss_uint32 A0;
+	etiss_uint32 A1;
+	etiss_uint32 A2;
+	etiss_uint32 A3;
+	etiss_uint32 A4;
+	etiss_uint32 A5;
+	etiss_uint32 A6;
+	etiss_uint32 A7;
+	etiss_uint32 S2;
+	etiss_uint32 S3;
+	etiss_uint32 S4;
+	etiss_uint32 S5;
+	etiss_uint32 S6;
+	etiss_uint32 S7;
+	etiss_uint32 S8;
+	etiss_uint32 S9;
+	etiss_uint32 S10;
+	etiss_uint32 S11;
+	etiss_uint32 T3;
+	etiss_uint32 T4;
+	etiss_uint32 T5;
+	etiss_uint32 T6;
+	etiss_uint32 *X[32];
+	etiss_uint32 ins_X[32];
+	etiss_uint32 FENCE[8];
+	etiss_uint8 RES[8];
+	etiss_uint8 PRIV;
+	etiss_uint32 DPC;
+	etiss_uint32 FCSR;
+	etiss_uint32 lpstart_0;
+	etiss_uint32 lpend_0;
+	etiss_uint32 lpcount_0;
+	etiss_uint32 lpstart_1;
+	etiss_uint32 lpend_1;
+	etiss_uint32 lpcount_1;
+	etiss_uint32 MSTATUS;
+	etiss_uint32 MIE;
+	etiss_uint32 MIP;
+	etiss_uint32 *CSR[4096];
+	etiss_uint32 ins_CSR[4096];
+	etiss_uint64 F[32];
+	etiss_uint32 RES_ADDR;
+};
+
+#pragma pack(pop) // undo changes
+typedef struct RV32IMAFDXCoreVHwlpV0 RV32IMAFDXCoreVHwlpV0; // convenient use of X instead of struct X in generated C code
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif