tools/litex_server.py: jtag/udp mode: add missing addr_width parameter

enjoy-digital · Dec 9, 2023 · 08ff003 · 08ff003
1 parent c1871ea
commit 08ff003
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/litex/tools/litex_server.py b/litex/tools/litex_server.py
@@ -231,7 +231,7 @@ def main():
         jtag_uart = JTAGUART(config=args.jtag_config, chain=int(args.jtag_chain))
         jtag_uart.open()
         print("[CommUART] port: JTAG / ", end="")
-        comm = CommUART(os.ttyname(jtag_uart.name), debug=args.debug)
+        comm = CommUART(os.ttyname(jtag_uart.name), debug=args.debug, addr_width=int(args.addr_width))
 
     # UDP mode
     elif args.udp:
@@ -250,7 +250,7 @@ def main():
             exit()
         else:
             print("[CommUDP] ip: {} / port: {} / ".format(udp_ip, udp_port), end="")
-            comm = CommUDP(udp_ip, udp_port, debug=args.debug)
+            comm = CommUDP(udp_ip, udp_port, debug=args.debug, addr_width=int(args.addr_width))
 
     # PCIe mode
     elif args.pcie: