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bug fix
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Yilong Geng committed May 7, 2015
1 parent 7345906 commit 69e09d8
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Showing 2 changed files with 10 additions and 10 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -78,11 +78,11 @@ module axi_lite_regs
input s_axi_rready,

// Part 2: Register side signals
output [NUM_RW_REGS*C_S_AXI_DATA_WIDTH-1:0] rw_regs,
input [NUM_RW_REGS*C_S_AXI_DATA_WIDTH-1:0] rw_defaults,
output [NUM_WO_REGS*C_S_AXI_DATA_WIDTH-1:0] wo_regs,
input [NUM_WO_REGS*C_S_AXI_DATA_WIDTH-1:0] wo_defaults,
output [NUM_RO_REGS*C_S_AXI_DATA_WIDTH-1:0] ro_regs
output [NUM_RW_REGS*C_S_AXI_DATA_WIDTH:0] rw_regs,
input [NUM_RW_REGS*C_S_AXI_DATA_WIDTH:0] rw_defaults,
output [NUM_WO_REGS*C_S_AXI_DATA_WIDTH:0] wo_regs,
input [NUM_WO_REGS*C_S_AXI_DATA_WIDTH:0] wo_defaults,
output [NUM_RO_REGS*C_S_AXI_DATA_WIDTH:0] ro_regs
);

function integer log2;
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Original file line number Diff line number Diff line change
Expand Up @@ -70,11 +70,11 @@
output IP2Bus_Error,

// -- Register ports
output [NUM_WO_REGS*C_S_AXI_DATA_WIDTH-1 : 0] wo_regs,
input [NUM_WO_REGS*C_S_AXI_DATA_WIDTH-1 : 0] wo_defaults,
output [NUM_RW_REGS*C_S_AXI_DATA_WIDTH-1 : 0] rw_regs,
input [NUM_RW_REGS*C_S_AXI_DATA_WIDTH-1 : 0] rw_defaults,
input [NUM_RO_REGS*C_S_AXI_DATA_WIDTH-1 : 0] ro_regs
output [NUM_WO_REGS*C_S_AXI_DATA_WIDTH : 0] wo_regs,
input [NUM_WO_REGS*C_S_AXI_DATA_WIDTH : 0] wo_defaults,
output [NUM_RW_REGS*C_S_AXI_DATA_WIDTH : 0] rw_regs,
input [NUM_RW_REGS*C_S_AXI_DATA_WIDTH : 0] rw_defaults,
input [NUM_RO_REGS*C_S_AXI_DATA_WIDTH : 0] ro_regs
);

function integer log2;
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